Bias voltage generating circuit

Details Bias voltage generating circuit Bias voltage generating circuit

1992-07-29

1994-03-22

Stephan, Steven L.

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

3072968, 36518909, G05F 316

Patent

active

052968014

ABSTRACT:
A bias voltage generating circuit supplies a bias voltage to a memory's bit lines. One end of a first transistor is connected to a first power supply. The first transistor conducts in response to a control signal. A second transistor is connected to another end of the first transistor. Another end of the second transistor and a gate of the second transistor are connected to an output node. One end of a third transistor and a gate connected to the output node. One end of a fourth transistor and a gate are connected to a second end of the third transistor. A second end of the fourth transistor is connected to a second power supply. One end of a fifth transistor is connected to the first power supply. The fifth transistor also conducts in response to the control signal. A sixth transistor is connected to a second end of the fifth transistor. A second end of the sixth transistor is connected to the output node and the gate of the sixth transistor is connected to a potential source. A seventh transistor is connected to the output node. A second end of the seventh transistor is connected to a ground potential. The seventh transistor also conducts in response to the control signal. The output node outputs a bias voltage to the bit lines when the control signal is activated, and is grounded through the seventh transistor when the control signal is non-activated.

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Ohtsuka, Nobuaki et al; ISSCC Digest of Technical Papers, dated Feb. 1991, vol. 34, pp. 262-263.
"FPM 16.1: A 60 ns 16 Mb Flash EEPROM (FIG. 6)" and FPM 16.2: A 62 ns 16 Mb CMOS EPROM (FIG. 5), ISSCC Digest of Technical Papers, 1991, p. 326.
S. Atsumi, et al., "Session 4: Non-Volatile and Fast Static Memories; WPM 4.2: A 16 ns 1 Mb CMOS EPROM," ISSCC Digest of Technical Papers, Feb. 1990, pp. 58-59, 265.
Y. Ohshima, et al., "Process and Device Technologies for 16 mBIT EPROMS with Large-Tilt-Angle Implanted P-Pocket Cell," IEDM Technical Digest, Dec. 1990, pp. 5.2.1-5.2.4(95-98).

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