Bias signal generator in radio receiver

Telecommunications – Receiver or analog modulated signal frequency converter – Signal selection based on frequency

Reexamination Certificate

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Details

C455S245100, C455S260000, C455S314000

Reexamination Certificate

active

06278866

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to radio wave receivers and, in particular, to a receiver formed as a single integrated circuit.
BACKGROUND
Radio receivers, such as amplitude modulation (AM) type receivers, are well known. It is desirable for cost and size reasons to implement such receivers on a single integrated circuit chip. However, obstacles have prevented a practical AM receiver from being implemented on a single chip.
SUMMARY
A single chip superheterodyne AM receiver is disclosed herein. Pin count may be 4 or more. The receiver is a OOK (ON-OFF keyed) Receiver IC for remote wireless applications. This device is an “antenna-in, data-out” monolithic device. All RF and IF tuning is accomplished automatically within the IC, which eliminates manual tuning, and reduces production costs. Receiver functions are completely integrated. The result is a highly reliable yet extremely low cost solution for high volume wireless applications. Because the receiver is a true single-chip radio receiver, it is extremely easy to apply, minimizing design and production costs, and improving time to market.
The receiver uses a novel architecture that allows the receiver to demodulate signals over a wide RF band, which eliminates the need for manual tuning. This is referred to as a swept LO mode. This also significantly relaxes the frequency accuracy and stability requirements of the Transmitter, allowing the receiver to be compatible with both SAW-based and LC-based transmitters. The receiver sensitivity and selectivity are sufficient to provide low bit error rates for decode ranges over 100 meters, equaling the performance of other more expensive solutions.
All tuning and alignment are accomplished on-chip with a reference frequency provided by a low-cost ceramic resonator or an externally supplied clock reference. The receiver performance is insensitive to data modulation duty cycle. The receiver may be used with such coding schemes as Manchester or 33/66% PWM.
To prevent noise from the clock reference decreasing the sensitivity of the receiver, the IF filter is tuned such the no integer multiple or integer divisor frequency of the timing reference occurs in the IF pass band.
All post-detection (demodulator) data filtering is provided on the receiver chip, so no external filters need to be designed. Any one of four filter bandwidths may be selected externally by the user. Bandwidths range from 0.6 kHz to 4.8 kHz in binary steps.
The various filters and demodulator have frequency characteristics based on the output of an internal timing generator which receives clock signals from an external reference. Therefore, tuning of the filters and demodulator may be accomplished by changing the external reference frequency.


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patent: 5710997 (1998-01-01), Okanobu
patent: 5933769 (1999-08-01), Kaneko
patent: WO 98/49779 (1998-11-01), None

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