Bias scheme for achieving voltage independent capacitance

Details Bias scheme for achieving voltage independent capacitance Bias scheme for achieving voltage independent capacitance

1987-05-15

1988-11-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307304, 357 14, 357 51, H03K 326, H03K 3353, H01L 2708, H01L 2978

Patent

active

047868287

ABSTRACT:
Described is a capacitive structure that can be fabricated with a digital MOS (Metal Oxide Semiconductor) process. The capacitive structure is comprised of two enhancement mode FET devices electrodes connected in series via their gate electrodes. The source and drain electrodes of each FET device are connected together. A third FET device, biased to operate within the linear or resistive region of its characteristic curve, is connected to the gate electrodes of the enhancement mode FET devices. The structure provides a voltage independent capacitor.

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