Bias method and circuit for distortion reduction

Details Bias method and circuit for distortion reduction Bias method and circuit for distortion reduction

2001-11-15

2003-03-11

Cunningham, Terry D. (Department: 2816)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S289000, C327S530000, C327S247000

Reexamination Certificate

active

06531924

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related generally to transistor circuits and, more particularly, to a bias method and circuit for distortion reduction.
BACKGROUND OF THE INVENTION
Transistor amplifiers and mixers are commonly used building blocks of analog circuits operating at frequencies ranging from audio to radio frequencies (RF). Generally, these circuits are required to minimally distort the signal they operate on to preserve the information carried by the signal.
The signal distortion in active circuits is generated by nonlinearities of the transistor. Consider a simple common-source NMOS amplifier and its equivalent circuit shown in
FIGS. 1A and 1B
, respectively. In
FIG. 1A
, M
1
is an NMOS transistor, C is a direct current (DC) blocking capacitor, and R
L
is a drain bias resistor. The equivalent circuit of
FIG. 1B
is an ideal model of the circuit of FIG.
1
A. In
FIG. 1B
, V
GS
is the gate-source voltage and I
D
is the drain current of M
1
. The drain current I
D
is a function of V
GS
. For proper operation, the gate of the transistor M
1
should be biased above the threshold voltage to allow a nonzero DC drain current to flow through M
1
. The gate
A commonly used prior-art bias circuit is shown in
FIG. 2
where a transistor M
2
is a scaled version (replica) of the transistor M
1
with the same gate length but a narrower width. Also shown in
FIG. 2
is a reference current source, I
REF
, and a bias resistor, R
B
, that isolates the bias circuit from the amplifier input at the operating frequency of the amplifier. The drain of the transistor M
1
is biased in the saturation region for high gain. Ideally, the transistor M
1
operates as a linear voltage-controlled current source having the following characteristics:
I
D
=g
m
(
V
GS
−V
TH
)  (1)
where V
TH
is the threshold voltage of the transistor M
1
and g
m
is the bias-independent coefficient called transconductance in units amperes per volt (A/V).
For further analysis, it is convenient to separate the DC values of I
D
and V
GS
from their alternating current (AC) values using the following relations:
I
D
=I
D0
+i
D
V
GS
=V
GS0
+v
GS
I
D0
=g
m
(
V
GS0
−V
TH
).  (2)
where I
D0
is the DC drain current and V
GS0
is the DC gate-source voltage of M
1
generated by the bias circuit. In equation (2) v
GS
is the AC gate-source voltage equal to the input signal voltage (v
IN
) and i
D
is the AC drain current. Equation (1) can be written in terms of the introduced AC values as follows:
i
D
=g
m
v
GS
  (3)
Where all terms have been previously defined.
When the AC input signal v
IN
is applied to the circuit, the transistor M
1
generates an output AC current equal to g
m
v
IN
that creates a voltage drop across the drain-bias resistor R
L
equal to −g
m
v
IN
R
L
. This voltage across the drain-bias resistor R
L
is the output signal of the amplifier and −g
m
R
L
is its gain.
In the ideal amplifier illustrated in
FIGS. 1A and 1B
, the output signal is a scaled version of the input signal (i.e., there are no spurious responses of the system). The spectrum of the output signal has the same frequency components as the input signal.
Unfortunately, the transconductance of a real-life transistor is not a constant but a function of the input bias voltage. This function is often described by a sophisticated equation or a system of equations. To simplify circuit analysis, this function is replaced by its Taylor series expansion near V
GS0
as follows:
g
m
=g
1
+g
2
v
GS
+g
3
v
GS
2
+  (4a)
where g
1
, g
2
and g
3
are the expansion coefficients equal to:
g
1
⁡
(
V
GS
)
=
ⅆ
I
D
ⅆ
V
GS
g
2
⁡
(
V
GS
)
=
1
2
⁢
ⅆ
2
⁢
I
D
ⅆ
V
GS
2
=
1
2
⁢
ⅆ
ⅆ
V
GS
⁢
(
ⅆ
I
D
ⅆ
V
GS
)
=
1
2
⁢
ⅆ
g
1
⁡
(
V
GS
)
ⅆ
V
GS
g
3
⁡
(
V
GS
)
=
1
6
⁢
ⅆ
3
⁢
I
D
ⅆ
V
GS
3
=
1
3
⁢
ⅆ
g
2
⁡
(
V
GS
)
ⅆ
V
GS
(4b)
Substituting this g
m
expansion into equation (3) above, we get the following expression for the output current of a real-life NMOS transistor:
 
i
D
=g
1
v
GS
+g
2
v
GS
2
+g
3
v
GS
3
+  (5)
This expansion is often called a power series. The first term in the series is called a linear term and represents the desired function of the transistor (e.g., the transistor M
1
). The second term is called the 2
nd
-order nonlinearity. The third term is called the 3
rd
-order nonlinearity, etc. The nonlinearities are not desirable since they generate spurious responses that interfere with the desired signal.
There are several well known techniques to reduce the circuit spurious responses relative to its desired fundamental response. These techniques are often referred to as the linearization techniques. The simplest and widely-used technique is based on the fact that the 2
nd
and 3
rd
-order expansion coefficients of the FET output current, g
2
and g
3
, decrease relative to the linear transconductance g
1
at gate-to-source voltages much larger than the threshold voltage. So, selecting large-enough V
GS0
results in much smaller spurious responses relative to the fundamental response of the circuit. Unfortunately, this technique increases the DC current consumption of the circuit which may not be acceptable for some applications (e.g., battery operated devices).
Another technique is based on the fact that, for many field-effect transistors, there are particular input bias voltages at which either the 2
nd
or the 3
rd
-order expansion coefficient is zero. These bias voltages are typically close to the threshold voltage and, therefore, don't result in a large DC drain current. If a transistor is biased at such a voltage, theoretically it generates zero 2
nd
or 3
rd
order distortion. It is possible to calculate a bias voltage at which g
2
or g
3
is zero from the simulated or measured transfer characteristic of the transistor. The calculated bias voltage will only be optimum for either a typical transistor for which the model was extracted or the measured transistor-sample. It will also be optimum only at a specific temperature at which the transfer characteristic was simulated or measured. It possible to design a bias circuit that generates this calculated gate-to-source voltage at which g
2
or g
3
is zero using a resistive divider for example. However, it will not satisfactorily eliminate the corresponding distortion as the operating temperature changes or the parameters of the transistor manufacturing process drift.
Accordingly, it can be appreciated that there is a significant need for a bias circuit that eliminates undesirable distortion components independent of temperature fluctuations and manufacturing process drifts. The present invention provides this, and other advantages, as will be apparent from the following detailed description and the accompanying figures.
SUMMARY OF THE INVENTION
The present invention is embodied in a method and circuit for biasing a transistor. The transistor to be biased has a transfer characteristic that may be characterized by a linear or first-order term that describes a straight line and nonlinear or higher-order terms, such as 2
nd
-order and 3
rd
-order nonlinearities, that describe the deviations of the transfer characteristic from the straight line. The inventive method generates a direct current signal proportional to a selected nonlinearity of the transistor and uses the DC signal to generate the bias voltage of the transistor at which the selected nonlinearity is zero.
In one example, the selected nonlinearity is a 2
nd
-order nonlinearity and the DC signal comprises first, second and third portions. The first, second and third portions are combined to form the DC signal. In another example, the selected nonlinearity is a 3
rd
-order nonlinearity and the DC signal comprises first, second, third and fourth portions. The first, second, third and fourth portions are combined to form the DC signal.
The method may also include providing a mirr

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