Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-12-03
2004-06-08
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S540000, C327S543000, C323S315000
Reexamination Certificate
active
06747507
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to bias generators for self biased phase locked loops.
BACKGROUND OF THE INVENTION
A Maneatis self-biased phase locked loop (PLL) architecture is based on the prior art self-biasing techniques shown in FIG.
1
. The circuit of
FIG. 1
includes amplifier A
1
; PMOS transistors MP
1
, MP
2
, MP
3
, and MP
4
; NMOS transistors MN
1
, MN
2
, MN
3
, and MN
4
; and source voltages VDD and VSS. It is very challenging to maintain the stability of this prior art bias generator over process, temperature, and supply variation. Instability in the bias generator will result in clock jitter. Conventionally, feedback-compensation using a resistor and capacitor is used to improve the stability. However, these components sometimes occupy significant silicon area and increase cost.
The bias generator shown in
FIG. 1
generates the signals at nodes VCP and VCN, which are used to bias a prior art voltage controlled oscillator (VCO) delay buffer cell shown in FIG.
2
. The circuit of
FIG. 2
includes PMOS transistors MP
5
, MP
6
, MP
7
, and MP
8
; NMOS transistors MN
5
, MN
6
, and MN
7
; input nodes VIN− and VIN+; and output nodes VO+ and VO−. The bias generator uses a half-buffer replica and a differential amplifier A
1
to keep the current through the VCO delay cell constant, by forcing the voltage at node VCP equal to control voltage VCTRL. The amplifier A
1
adjusts the voltage at node VCP to reject supply and substrate voltage noises.
One of the challenges involved in the design of the bias. generator is to maintain stability for applications requiring the VCO to function over a wide frequency range. A block diagram of the bias generator is shown in FIG.
3
. H
3
(S), H
2
(S) and A(S) represent transfer functions associated respectively with transistors MN
3
and MP
2
and the amplifier A
1
. The circuit has two main poles and a zero:
P
1
=
-
1
ClR
o
,
P
2
=
-
gm
4
+
gds
3
+
gds
4
Cl
2
and
Z
1
=
Gm
.
gm
2
R
o
-
gm
3
gm
3
ClR
o
where Gm represents the transconductance of the input transistor of amplifier A
1
, gm
4
represents the transconductance of transistor MN
4
, gm
2
represents the transconductance of transistor MN
2
, gm
3
represents the transconductance of transistor MN
3
, gds
3
represents the conductance of transistor MN
3
and gds
4
represents the conductance of transistor MN
4
. P
1
and P
2
are the two main poles, and Z
1
is the zero. Cl and Cl
2
represent the load on nodes VCN and VFB respectively and R
o
is the output resistance of amplifier A
1
.
For applications operating over a wide frequency range, and thus a wide control voltage VCTRL range, the location of the poles and zero are always changing, making stability a concern. For example, there is a possibility that the zero, which is in the right half plane, will move to the left half plane for Gmgm
2
R
o
<<gm
3
. Furthermore, for gm
3
=Gm, and assuming gm4>>(gds
4
+gds
3
), the poles and zero locations become:
P
1
=
-
1
ClR
o
,
P
2
=
-
gm
4
Cl
2
and
Z
1
=
gm
2
Cl
The new poles and zero locations indicate the presence of a doublet that may deteriorate the time response.
One of the prior art solutions is RC compensation, but this does not eliminate the pole-zero doublet. Also, RC compensation may work well for a given control voltage but with different control voltage VCTRL, the transconductance of transistor MN
2
varies making RC compensation difficult to realize for a wide range of control voltages.
SUMMARY OF THE INVENTION
A bias generator circuit with improved phase margin without RC compensation includes: a first transistor; a second transistor coupled in parallel with the first transistor; an amplifier having a first input coupled to the first transistor and to a gate of the second transistor, and a second input coupled to a control voltage node; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the third transistor and having a gate coupled to an output of the amplifier; a fifth transistor; a sixth transistor coupled in parallel with the fifth transistor; a seventh transistor coupled in series with the fifth transistor; and an eighth transistor coupled in series with the seventh transistor and having a gate coupled to a gate of the fourth transistor. In order to maintain the bias generator stability for. different biasing conditions, the feed-forward path is removed by diode connecting the second transistor instead of connecting the gate of the second transistor to the control voltage node.
REFERENCES:
patent: 5856742 (1999-01-01), Vulih et al.
patent: 5900773 (1999-05-01), Susak
patent: 6150872 (2000-11-01), McNeill et al.
patent: 6181196 (2001-01-01), Nguyen
patent: 6380723 (2002-04-01), Sauer
patent: 2002/0093325 (2002-07-01), Ju
Chen Wenliang
Sadate Aline C.
Brady III W. James
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Bias generator with improved stability for self biased phase... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bias generator with improved stability for self biased phase..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bias generator with improved stability for self biased phase... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3333769