Bias for electrostatic discharge protection

Details Bias for electrostatic discharge protection Bias for electrostatic discharge protection

2008-05-27

2008-05-27

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07379281

ABSTRACT:
An electrostatic discharge protection circuit adapted to reduce an electrostatic discharge event on a line of an integrated circuit. The protection circuit includes an NMOS transistor having a source contact that is electrically connected to the line. A drain contact is electrically connected to a logical low voltage, and a gate contact is also electrically connected to the logical low voltage, through a resistor. A substrate bias pump is electrically connected to a back gate of the NMOS transistor, where the bias pump provides a steady state direct current negative bias during normal operation of the integrated circuit when there is no electrostatic discharge event.

REFERENCES:
patent: 6724592 (2004-04-01), Tong et al.
Charvaka Duvvury et al,Substrate Pump NMOS for ESD Protection Applications, ESD Association, 2000, no month.

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