Bias feed network arrangement for balanced lines

Details Bias feed network arrangement for balanced lines Bias feed network arrangement for balanced lines

2002-04-03

2003-09-16

Wells, Kenneth B. (Department: 2816)

Wave transmission lines and networks

Long line elements and components

Strip type

C455S333000

Reexamination Certificate

active

06621385

ABSTRACT:

FIELD OF INVENTION
This invention relates to balanced line circuits and more particularly to a bias feed network for a balanced line circuit.
BACKGROUND OF INVENTION
A balanced transmission line or balanced line is basically a transmission line that consists of two conductors which are capable of being operated so that the voltages of the two conductors at any transverse plane are equal in magnitude and opposite in polarity with respect to ground. In this manner, the currents in the two conductors are then equal in magnitude and opposite in direction. A balanced line is typically employed in semiconductor circuits for high frequency operation.
For example, on a lossy substrate, such as silicon, balanced lines are useful for implementing circuits. Such balance transmission lines prevent magnetic fields from interfering with circuit operation. Balanced lines operate to provide lower losses compared to microstrip (MS) or coplanar waveguide (CPW) structures on conductive silicon. In fabricating silicon integrated circuits, via-holes through the silicon substrate are not employed. Such via-holes are employed in gallium arsenide (GaAs) substrates and other substrates to enable one to go from the top surface of a circuit substrate to a bottom surface of the circuit substrate or from one layer to another. In silicon, via-holes in the silicon substrate (unlike gallium arsenide substrates) do not exist and since the balanced lines do not require via-holes, they are ideal for use in lossy silicon substrates. The operation of the balanced line minimizes interference.
SUMMARY OF THE INVENTION
There is disclosed a circuit configuration for introducing bias in balanced lines capable of high frequency operation. The circuit configurations are positioned on top and bottom layers formed on a semiconductor substrate. The circuit includes two balanced metallized lines positioned on the substrate. Each metallized line has a serpentine line configuration connected thereto. The space between the lines is a virtual ground. The serpentine line configurations are congruent with the elements on the substrate layers to provide a completed circuit. The elements are coupled to a central metallic area, which in turn is coupled to a bias line through an open-line stub, which extends beyond the virtual ground and which provides equal capacitive coupling to the balanced lines on the top surface. In this manner, the balanced line configuration includes capacitors and inductors which are symmetrically distributed and which provide resonance at the designed operating frequency. The bias line thus formed is RF grounded due to the virtual ground and is disconnected from the actual balanced lines. The positioning of the circuit enables excellent isolation at the designed operating frequency. The circuit configuration is relatively small and compact and can be used in conjunction with lossy substrates to provide optimum balancing of such lines.


REFERENCES:
patent: 5752182 (1998-05-01), Nakatsuka et al.

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