Bias distribution circuit and method using FET and bipolar

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307310, 307570, 3072966, G06G 710

Patent

active

051553945

ABSTRACT:
A biasing circuit and method of producing a biasing voltage particularly suitable for integrated circuits combining MOS and bipolar technology. The circuit includes an NMOS transistor which produces a gate-source reference voltage when drain current is supplied to the transistor. The reference gate-source voltage is coupled to the output of the circuit at a reduced impedance level so as to increase noise immunity. The coupling circuit preferably includes two NPN bipolar transistors. The NPN transistors add and subtract identical base-emitter junction voltages to the reference voltage so that the magnitude of the reference voltage is unchanged. An NMOS transistor, having a gate-source voltage equal to the reference voltage, is also connected to the output for reducing the output impedance of the circuit.

REFERENCES:
patent: 4438349 (1984-03-01), Shoji
patent: 4461991 (1984-07-01), Smith
patent: 4492929 (1985-01-01), Vyne
patent: 4532467 (1985-07-01), Mensink
patent: 4608530 (1986-08-01), Bacrania
patent: 4656374 (1987-04-01), Rapp
patent: 4658137 (1987-04-01), McGowan
patent: 4659944 (1987-04-01), Miller

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