Bias control circuit for power amplifier

Details Bias control circuit for power amplifier Bias control circuit for power amplifier

2003-03-11

2004-06-01

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S285000

Reexamination Certificate

active

06744321

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a bias control circuit for a power amplifier; and, more particularly, to a bias control circuit capable of improving a power added efficiency of a power amplifier.
BACKGROUND OF THE INVENTION
In a wireless mobile communications system, a power amplifier is a key component that determines a lifetime of a battery in a mobile terminal, e.g., a conventional CDMA mobile handset. Thus, the power amplifier is required to be of a high efficiency characteristic in order to increase the lifetime of the battery. The power added efficiency of the conventional power amplifier is normally highest when an output power thereof is at its highest level, decreases as the output power falls off from the highest level of, e.g., 30 dBm. However, the power amplifier is usually operated at an output power ranging from, e.g., −15 to 15 dBm. Therefore, there have been proposed various schemes capable of improving the power added efficiency of the power amplifier at such low output power range, by way of increasing a quiescent current in a high output power mode, while decreasing the bias current in a low output power mode.
Such methods include a technique for controlling Vcc (DC supply) or VB (base bias voltage) of a bias circuit, and a dual bias control technique for controlling both Vcc and VB. All of these techniques adopt a DC-to-DC converter, which requires a DSP (digital signal processor) or an RF (radio frequency) coupler for the control thereof, specifically the RF coupler being adopted in case the control is implemented in an RF range.
The technique for controlling Vcc mentioned above is directed to reduce DC power consumption when the power amplifier is in the low output power mode. To be specific, Vcc is reduced in the low output power mode but increased in the high output power mode by using the DC-to-DC converter to thereby improve the efficiency of the power amplifier.
The technique for controlling VB mentioned above accomplishes the power added efficiency improvement by way of adopting the DC-to-DC converter to control VB. To be more specific, in the low output power mode, the DC-to-DC converter reduces the bias current and thus, decreases the DC power consumption, while, in the high output power mode, the DC-to-DC converter increases the bias current.
The dual bias control technique increases the power added efficiency of the power amplifier by simultaneously controlling both Vcc and VB in a manner described above.
All of the above-mentioned conventional techniques adopt the DC-to-DC converter to control the DC power consumption depending on the output power mode of the power amplifier. These conventional techniques, however, have a drawback in that it is very difficult to install such components as the RF coupler and the DC-to-DC converter within a highly miniaturized module of power amplifier having a size of, e.g., 6×6 mm
2
. Thus, it may be desired to develop a method for increasing the power added efficiency of the power amplifier in the low output power mode without an additional component such as the DC-to-DC converter.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a cost-effective miniaturized bias control circuit capable of effectively controlling DC power consumption in a high/low output power mode to thereby greatly improve a power added efficiency in the low output power mode without adversely affecting the power added efficiency in the high output power mode.
In accordance with the present invention, there is provided a bias control circuit for a power amplifier including an RF amplifier having a power transistor for power amplification, including: a bias circuit having a first active bias transistor and connected to a predetermined Vref pin to provide the power transistor with a first bias current; and a bias current control circuit having a second active bias transistor and a diode, the diode being prepared between a Vcon pin and a collector of the second active bias transistor to thereby control a second bias current of the power transistor.


REFERENCES:
patent: 6486739 (2002-11-01), Luo
patent: 6492875 (2002-12-01), Luo et al.
patent: 6549076 (2003-04-01), Kuriyama

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