Amplifiers – Signal feedback – Combined with control of bias voltage of signal amplifier
Patent
1975-12-22
1976-10-05
Rolinec, R. V.
Amplifiers
Signal feedback
Combined with control of bias voltage of signal amplifier
330 13, 330 15, 330 22, 330 40, H03F 316
Patent
active
039847810
ABSTRACT:
A power amplifier is constituted by a complementary pair of one N channel and one P channel unsaturated junction type FET's constructing a single ended pushpull circuit, the N channel FET having a drain connected to the positive terminal of a first dc power source of a predetermined voltage and a source connected via a load to a ground potential, and the P channel FET having a drain connected to the negative terminal of the first dc power source and a source connected via the load to the ground potential. The gate potentials of the complementary pair of FETs constituting the power amplifier are controlled by a bias control circuit constructed of a complementary pair of one PNP type and NPN type bipolar transistors, the PNP type bipolar transistor having a collector coupled to the gate of the N channel FET and connected via a first resistor to the negative terminal of a second dc power source with its voltage predetermined and varied at substantially the same rate as that of the first dc power source and a base connected to the collector thereof via a second resistor, and the NPN type bipolar transistor having a collector coupled to the gate of the P channel FET and connected via a third resistor of the same resistance value as the first resistor to the positive terminal of the second dc power source and a base connected to the collector thereof via a fourth resistor of the same resistance value as the second resistor, the bases of the bipolar transistors being also interconnected via a common resistor and the emitters thereof being coupled in common to one terminal of an input audio signal source having the other terminal connected to the ground potential via respective resistors of the same resistance value, whereby the amounts of drain current flowing into the complementary pair of FET's are each maintained substantially constant, even if the voltage levels of the first and second dc power source are fluctuated.
REFERENCES:
patent: 3921089 (1975-11-01), Tsurushima
Dahl Lawrence J.
Rolinec R. V.
Sansui Electric Co. Ltd.
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