Bias condition and X-decoder circuit of flash memory array

Details Bias condition and X-decoder circuit of flash memory array Bias condition and X-decoder circuit of flash memory array

1998-09-24

1999-11-02

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36523006, 36518511, 36518527, 365218, 36523003, G11C 1604

Patent

active

059782773

ABSTRACT:
New bias conditions for flash memory cells and X-decoder circuits for providing the bias conditions. In an erasing operation, a positive high voltage is provided to the bulk and a negative high voltage is provided to the control gate for establishing a sufficient electric field to induce electron tunneling effect. In an operation for repairing a cell's threshold voltage, the biased voltages are reversed. A first X-decoder circuit structure is presented for supplying positive and negative high voltages to the memory cells for block erasing or repairing. The first X-decoder circuit structure has a plurality of X-decoder blocks each being constructed in a separated X-decoder well, and the memory cells are fabricated in a separate common array well. A second X-decoder circuit structure is presented to provide an appropriate bias condition for erasing or repairing a small sector of word lines. For the second X-decoder circuit structure, each memory block is fabricated in a separated array well. Separated X-decoder wells are constructed to provide voltages to the word lines of memory blocks. Every word line in a memory block has an X-decoder driver so that the word line can be erased or repaired individually. A new layout is also presented for the construction of the X-decoder circuits.

REFERENCES:
patent: 5701272 (1997-12-01), Brennan, Jr.
patent: 5848000 (1998-12-01), Lee et al.
patent: 5856942 (1999-01-01), Lee et al.

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