Bias circuits for depletion mode field effect transistors

Details Bias circuits for depletion mode field effect transistors Bias circuits for depletion mode field effect transistors

2000-06-15

2001-09-11

Shingleton, Michael B (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S277000, C330S288000

Reexamination Certificate

active

06288613

ABSTRACT:

This invention relates to bias circuits for depletion mode field effect transistors (FETs).
BACKGROUND
is well known to use depletion mode FET circuits for operation at high frequencies, for example in radio frequency amplifiers and mixers. Such FET circuits typically comprise metal-semiconductor FETs (MESFETs) using semiconductors such as gallium arsenide (GaAs) or indium phosphide; however, the same comments and this invention can also be applied to other types of depletion mode FETs, including for example metal-oxide-semiconductor FETs (MOSFETs) and junction FETs. For various reasons, process variations which inevitably occur in the manufacture of such FETs and integrated circuits including such FETs result in varying characteristics of the manufactured devices.
For depletion mode FETs it has been recognized that enhanced and consistent RF operation can be established by controlling DC characteristics of the FETs, and in particular by controlling a bias voltage supplied to each FET. By providing an appropriate gate bias, a desired drain-source current of the FET can be determined and maintained, resulting in a predictable RF performance. Consequently, a useful yield of manufactured devices with relatively stable characteristics can be provided by a bias circuit which supplies to each FET a bias voltage to compensate for process variations in the manufacturing process. Accordingly, such a bias circuit is desirably provided as part of an integrated circuit including the FET to be biassed, so that the FET and the bias circuit are subject to the same process variations.
In addition, it is desirable for the bias circuit to provide compensation for other factors, such as aging and temperature variation, which can otherwise adversely affect the operating characteristics of the FET. Alternatively, it may be desired to provide a PET which has a predetermined non-zero dependence of one of its parameters, e.g. drain-source current, with a parameter such as temperature, for example to compensate for a similar but opposite dependence of other circuits with which the FET is used.
Thus there is a need to provide a bias circuit for a depletion mode FET which can facilitate achieving such desires.
SUMMARY OF THE INVENTION
According to one aspect of this invention there is provided a bias circuit for providing a gate voltage for a first depletion mode FET (field effect transistor) to be controlled, the bias circuit comprising: a second depletion mode FET having similar characteristics to the first FET, the second FET having its gate coupled to its source for conducting a drain-source current via a resistor to produce a first voltage dependent on the drain-source current; and a comparator for comparing the first voltage with a reference voltage to produce said gate voltage in dependence upon differences between the first voltage and the reference voltage, so that an increase in said drain-source current of the second FET results in a change of said gate voltage of the first FET to reduce drain-source current of the first FET thereby to compensate for process variations of said first and second FETs.
Another aspect of the invention provides a bias circuit for providing a gate voltage for a first depletion mode FET (field effect transistor) to be controlled, the bias circuit comprising: a second depletion mode FET having similar characteristics to the first FET, the second FET having a source-follower configuration with its gate coupled to its source for conducting a drain-source current via a first resistor to produce a first voltage dependent on the drain-source current across the first resistor; a third depletion mode FET having its gate coupled to the first resistor to receive the first voltage, its source arranged to receive a reference voltage, and its drain connected to a second resistor for conducting drain-source current of the third FET via said second resistor to produce said gate voltage for the first FET at the drain of the third FET.
The invention also provides a method of compensating for process variations to which a first depletion mode FET is subject by controlling a gate voltage of the first FET, comprising the steps of: biassing a second depletion mode FET, subject to substantially the same process variations as the first FET, with an approximately zero gate-source voltage so that it conducts a drain-source current via a first resistor to produce a first voltage; supplying the first voltage and a reference voltage to the gate and source respectively of a third depletion mode FET whereby the third FET conducts a drain-source current via a second resistor coupled to the drain of the third FET; and deriving the gate voltage of the first FET from a junction between the drain of the third FET and the second resistor.


REFERENCES:
patent: 5506544 (1996-04-01), Staudinger et al.
patent: 5724004 (1998-03-01), Reif et al.
patent: 5808515 (1998-09-01), Tsuruoka et la.
patent: 5892400 (1999-04-01), Van Saders et al.
patent: 5994968 (1999-11-01), Kawai et al.

Affiliated with

Also associated with

Rating

Bias circuits for depletion mode field effect transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bias circuits for depletion mode field effect transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bias circuits for depletion mode field effect transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2527032