Bias circuitry for nonvolatile memory array

Details Bias circuitry for nonvolatile memory array Bias circuitry for nonvolatile memory array

1990-12-21

1992-07-21

Clawson, Jr., Joseph E.

Static information storage and retrieval

Powering

365104, 365185, 36523006, 36518909, G11C 514

Patent

active

051329336

ABSTRACT:
A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline. The circuit includes a common node; a resistor means coupled between the common node and each of the source- and drain-column lines; a drain-select means coupled to each drain-column line for transmitting, during a read cycle, a first preselected bias voltage lower than a supply voltage to the selected drain-column line; a source-select means coupled to each source-column line for transmitting, during the read cycle, a second preselected bias voltage to the one non-selected source-column line, the one non-selected source-column line coupled to a cell sharing the selected drain-column line and the selected wordline; and reference-select means for connecting, during the read cycle, the source-column lines, except the one non-selected source-column line, to reference potential. The sense amplifier and the driver circuit each include at least three transistors and have outputs coupled to drain-column lines and source-column lines, respectively, of the memory array.

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B. Ashmore et al, "A 20 ns 1MB CMOS Burstmode Eprom," 1989 IEEE Int. S-S ckts Conf., Feb. 15, 1989 pp. 40-41.
N. Ohtsuka et al., "A 62 ns 16 Mb CMOS Eprom W. Address Trans. Det. Tech," 1991 IEEE Int. S-S ckts Conf., Feb. 15, 1991, pp. 262-263.

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