Bias circuitry for content addressable memory cells of a floatin

Details Bias circuitry for content addressable memory cells of a floatin Bias circuitry for content addressable memory cells of a floatin

1992-03-31

1993-11-30

Fears, Terrell W.

Static information storage and retrieval

Powering

365900, 365203, G11C 1300

Patent

active

052672131

ABSTRACT:
A low power bias voltage generation circuitry for content addressable memory cells for a nonvolatile memory is described. The bias circuitry is comprised of a source follower pair and two cascaded high impedance voltage dividers. The source follower pair acts as a positive feedback loop coupling between the two high impedance voltage dividers for relatively quickly charging and settling the output node to a predetermined voltage level. The first high impedance voltage divider can relatively quickly provide an input signal to trigger the small-input-load second high impedance voltage divider. The second high impedance voltage divider comprised of two high impedance diode stacks allows most current drawing from the power supply to drive a relatively large output loading during switching. Both first and second high impedance voltage dividers help keep the DC current of the circuit to a relatively low level which helps to reduce the total power consumption of the circuit.

REFERENCES:
patent: 5047985 (1991-09-01), Mayaji

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