Bias circuit for use in quadrature modulator

Details Bias circuit for use in quadrature modulator Bias circuit for use in quadrature modulator

2000-05-25

2001-09-11

Mis, David (Department: 2817)

Modulators

Phase shift keying modulator or quadrature amplitude modulator

C375S308000

Reexamination Certificate

active

06288619

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to quadrature modulator and, in particular, to a bias circuit for use in the quadrature modulator.
As the manner known in the art, a quadrature modulator is used as a digital modulator in a phase shift keying such as a quadrature phase shift keying (QPSK). The quadrature modulator is supplied with an in-phase input signal and a quadrature input signal from a digital transmuting part. The quadrature input signal has a phase which is different from that of the in-phase input signal by 90 degrees or &pgr; radlan. The quadrature modulator is also supplied with a local signal having a predetermined frequency from a local oscillator. In the manner known in the art, the quadrature modulator modulates the in-phase input signal and the quadrature input signal using the local signal to produce a modulated signal.
In the manner which will later be described in conjunction with
FIG. 1
, the quadrature modulator comprises first and second bias circuits and a phase modulating circuit The first bias circuit is supplied with the in-phase input signal as an input signal while the second bias circuit is supplied with the quadrature input signal as an input signal.
In the manner which will later be described in conjunction with
FIGS. 2 through 4
, a conventional bias circuit comprises an input capacitor, first through fourth resistors, a ground capacitor, a bias stabilizing resistor, and a matching load resistor. Each of the first and the second resistors has an end connected to a power supply terminal. The third resistor has, as a first node, an end connected to another end of the first resistor. The fourth resistor has, as a second node, an end connected to another end of the second resistor. Each of the third and the fourth resistors is grounded. The bias stabilizing resistor is connected between the first and the second nodes to make first and second DC bias voltages at the first and the second nodes substantially equal. The first through the fourth resistors have the same and high resistance.
On the other hand, the input signal is supplied to the bias circuit through a low pass filter for limiting a band of the input signal. The low pass filter has a low output impedance while the bias circuit has a high input impedance. In order to make the bias circuit and the low pass filter impedance-matching, the matching load resistor is connected to an output terminal of the low pass filter and a ground terminal.
As described above, the conventional bias circuit comprises the bias stabilizing resistor and the matching load resistor and it results in increasing the number of the resistors.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a bias circuit for use in a quadrature modulator, that is capable of decreasing the number of resistors constituting the bias circuit
Other objects of this invention will become clear as the description proceeds.
On describing the gist of this invention, it is possible to be understood that a bias circuit is for use in a quadrature modulator. The bias circuit has an input terminal supplied with an input signal through a low pass filter having an output impedance. The bias circuit has first and second nodes for producing a noninverted signal and an inverted signal, respectively. The bias circuit comprises an input capacitor disposed between Me input terminal and the first node, a first resistor disposed between a power supply terminal and the first node, a second resistor disposed between the power supply terminal and the second node, a third resistor disposed between the first node and a ground terminal, a fourth resistor disposed between the second node and the ground terminal, a ground capacitor disposed between the second node and the ground terminal, and a bias stabilizing resistor connected between the first and the second nodes. According to an aspect of this invention, in the above-understood bias circuit, the bias stabilizing resistor has a resistance value which is substantially equal to an impedance value of the output impedance of the low pass filter.


REFERENCES:
patent: 5428643 (1995-06-01), Razzell

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