Bias circuit for maintaining a constant value of...

Details Bias circuit for maintaining a constant value of... Bias circuit for maintaining a constant value of...

2001-01-31

2002-06-18

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S096000, C327S337000

Reexamination Certificate

active

06407623

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to integrated circuits and in particular to CMOS bias circuits for biasing operational amplifiers of switched capacitor (SC) circuits or other devices employing NMOS or PMOS differential pairs.
2. Description of the Related Art
Operational amplifiers containing differential pairs are commonly employed within integrated circuits as components of, for example, SC analog signal processing circuits. Bias circuits are employed in connection with the differential pairs of the operational amplifiers to ensure that certain characteristics of the operational amplifier remain substantially constant despite temperature changes or process variations. Examples include bias circuits for maintaining a constant current or a constant transconductance (g
m
) within the differential pair of the operational amplifier. A constant g
m
is more efficient than constant current. For operational amplifiers used in SC circuits, the operational speed of the SC circuit is limited primarily by the unity gain bandwidth of the operational amplifiers. More specifically, the settling time of the SC circuit is a strong function of the unity gain bandwidth of the operational amplifiers wherein the unity gain bandwidth is given by
ω
0
=
g
m
C
L
,
where g
m
is the transconductance of the operational amplifier and C
L
is the effective load capacitance.
Hence, bias circuits providing only a constant g
m
do not necessarily yield improved performance speed for SC circuits. Rather, a bias circuit providing a constant g
m
/C
L
is preferred. In the following, various conventional bias circuits for use with operational amplifiers are described and unity gain bandwidth issues arising with respect to the bias circuits are discussed.
FIG. 1
illustrates an exemplary operational amplifier
10
appropriate for use in a SC circuit. Operational amplifier
10
includes a differential pair of NMOS devices
12
and
14
and a differential pair of PMOS current mirror devices
13
and
15
. The four devices are interconnected, as shown, between a positive voltage source V
DD
and a node A. The pair of NMOS devices have gates connected to a pair of voltage input lines
16
and
18
, respectively. An output line
20
is connected to a node interconnecting NMOS device
14
and PMOS device
15
as shown. A capacitor
21
, providing a load capacitance of C
L
, couples the output signal to an external load
22
. To ensure that certain circuit characteristics such as current or g
m
remain constant despite temperature or process variations, the operational amplifier is biased by a bias signal provided along. a bias line
25
and applied to the gate of an additional NMOS device
24
connected between node A and ground.
FIG. 2
illustrates operational amplifier
10
of
FIG. 1
in combination with a bias circuit
26
for maintaining constant current despite temperature changes and process variations. Bias circuit
26
includes a current source
27
in combination with a single NMOS device
29
configured to operate as a current mirror. With this arrangement, the operational amplifier is biased to maintain constant current proportional to the current provided by current source
27
, independent of temperature changes and process variations.
However, the g
m
of the operational amplifier is not maintained as a constant. Rather the g
m
of the operational amplifier of
FIG. 2
is given by:
g
m
=
2
⁢
I
0
v
GS
-
V
T
,
where, I
0
is the bias current, V
GS
is the gate to source voltage of device
12
, and V
T
is the threshold of device
12
. V
T
changes with temperature and process variations. Thus g
m
varies due to temperature and process fluctuations. Moreover, for most applications, the load capacitance (C
L
) also changes due to process variations by about ±10%. Therefore, the unity gain bandwidth of an operational amplifier biased with a constant current source can change significantly due to g
m
and C
L
variations caused by temperature changes and process fluctuations. Hence, the speed performance of an SC circuit employing the operational amplifier is degraded.
FIG. 3
illustrates operational amplifier
10
of
FIG. 1
in combination with a bias circuit
30
for maintaining a constant g
m
despite temperature changes and process variations. Briefly, the bias circuit includes a pair of NMOS devices
32
and
34
connected between a pair of nodes B and C and ground, respectively. A pair of PMOS devices
33
and
35
are connected, respectively, between nodes B and C and a positive voltage source. Gates of NMOS devices
32
and
34
are connected to node B. Gates of PMOS devices
33
and
35
are connected to node C. A g
m
-setting resistor
36
is connected between the source of NMOS device
34
and ground. Resistor
36
is typically located off-chip to permit the resistance to be set after chip fabrication. In use, bias circuit
30
operates as a current mirror to generate a bias current that sets the g
m
's of NMOS devices
12
and
14
of the operational amplifier to an amount inversely proportional to the resistance of g
m
-setting resistor
36
. The bias circuit is, in effect, an MOS version of a self-biasing Widlar current source, well known in the art.
Thus, the bias circuit of
FIG. 3
substantially guarantees that the g
m
of the operational amplifier does not vary due to process and temperature variations, at least to the first order. More specifically, the Kirchoff voltage levels for the circuit are given by:
I
0
R+&ngr;
GS2
=&ngr;
GS1
.
Assuming a quadratic equation for the drain saturation current:
v
GS
-
v
T
=
(
Id
)
/
(
1
2
⁢
μ
⁢
 
⁢
C
OX
⁢
W
L
)
.
If threshold voltages of devices
32
and
34
of the bias circuit are assumed to be equal (ignoring body effects) then:
&ngr;
GS1
−V
T
=2(&ngr;
GS
−V
T
)
Hence:
I
0
R=½(V
GS1
−V
T
)
and thus,
g
m
=
2
⁢
I
0
v
GS1
-
V
T
=
1
R
.
Thus, disregarding body effects, the g
m
's of the devices of the operational amplifier are merely proportional to the resistance of g
m
-setting resistor
36
. Unfortunately, in practical integrated circuits, body effects can pose a significant problem. Briefly, body effects relate to a modification of the threshold voltage V
T
caused by a voltage difference between source and substrate. The change in voltage threshold is proportional to the square root of the voltage between the source and the substrate.
In the circuit of
FIG. 3
, the change in threshold voltage results in two separate problems. The first problem occurs from the variations in source voltage between NMOS devices
32
and
34
of the bias circuitry. Since the source of NMOS device
34
is at a different voltage from that of device
32
, the g
m
is not merely proportional to the resistance of resistor
36
but is instead given by the following equation:
g
m
=
1
+
1
+
2
·
B
·
R
·
vterr
2
⁢
R
where
B
=
μ
n
⁢
Cox
⁢
W
L
.
This formula for g
m
may be derived from the following set of equations:
&ngr;
gs1
=&ngr;
gs2
+I·R−&ngr;
terr
and since
vgs
=
2
·
I
B
-
v
T0
with
B
=
μ
n
⁢
Cox
⁢
W
L
.
then
2
·
I
B
=
1
2
⁢
2
·
I
B
+
I
·
R
-
vterr
.
solving for
I
=
1
2
·
B
+
2
B
+
R
·
vterr
2
⁢
R
yields
g
m
={square root over (2+L ·B·I)}
and finally
g
m
=
1
+
1
+
2
·
B
·
R
·
vterr
2
⁢
R
.
The second body effect problem occurs as a result of absolute differences between devices
32
and
34
of the bias circuitry and devices
12
and
14
of the operational amplifier. The absolute current generated in the bias circuit is proportional to the threshold voltage, and therefore any variances between the source voltages will result in a different g
m
value. Since the input common mode voltage to the operational amplifier is fixed, the source voltage of devices
12
and
14
will vary with process causing a non-tracking g
m
. As a result, tempe

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