Bias circuit for depletion mode field-effect transistors

Details Bias circuit for depletion mode field-effect transistors Bias circuit for depletion mode field-effect transistors

1999-12-23

2001-10-16

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S530000, C330S296000

Reexamination Certificate

active

06304130

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of depletion mode transistor circuits. More specifically, it pertains to a bias circuit for depletion mode field-effect transistors.
BACKGROUND OF THE INVENTION
It is well known that the DC characteristics of Field-Effect Transistors (FETs) in general, and GaAs Metal-Semiconductor FETs (Gallium Arsenide MESFETs) in particular, can not be controlled to arbitrarily tight tolerances. The FETs on a given wafer, and even within a given chip, will exhibit differences in DC and Radio Frequency (RF) characteristics, developed during processing of the FET. In the case of a MOSFET, these differences are due to changes in gate oxide thickness, channel doping and impurities in the channel and oxide. In the case of a GaAs MESFET, these differences are due to changes in gate length, impurities in the channel and different channel doping levels. Much of the evolution in circuit design over the past 50 years has dealt with designing circuits that are tolerant of these variations.
GaAs FETs have excellent high frequency characteristics, making them especially suitable for use at high frequencies in applications such as RF amplifiers and mixers. In these circuits, many traditional techniques that make circuits immune to device variations, such as differential circuitry, can not be used for various reasons. In particular, such techniques reduce dynamic range, increase power dissipation, degrade noise figure, degrade linearity and reduce efficiency.
In use, the gate of the FET must be biased for proper operation, in order to achieve maximum efficiency. Due to the above-described limitations on the circuit topologies used for high-frequency applications, many GaAs FET based circuits, even today, rely on very simple biasing circuitry, such as a constant drain bias voltage and a gate bias supplied by some form of a voltage source (which may or may not be controlled). If fixed voltage sources are used, the RF performance of the circuit may vary unacceptably because of differences in the FETs. The use of variable voltage sources (either factory adjusted or adjusted through a feedback loop) overcomes this problem, but is an expensive alternative.
A technique that is becoming more and more popular for biasing GaAs FET based circuits is known as the “tracking bias”, whereby a transistor (reference transistor) similar to the transistor being controlled (RF transistor) is connected in a circuit that has feedback for a stable operating point. Since the reference transistor does not operate at RF, several different circuit topologies (that are impossible to implement on a transistor that must handle RF signals) are possible. Since the reference transistor is similar to the RF transistor, the gate voltage that the reference transistor operates at is also suitable for the RF transistor. As long as the temperature of the two transistors is kept the same (and this will be the case if the transistors are located physically close to each other), a change in temperature is also handled appropriately. As long as the processing that the two transistors undergo is the same (and this will be the case if the transistors are located physically close to each other), process variations are handled appropriately.
With respect to the “tracking bias” technique, little power is wasted, as the reference transistor can be made quite small. Other advantages include:
There is no compromise in the design of the RF part of the circuit.
The circuitry is small and can be implemented in an ASIC very inexpensively.
No adjustments are required, and several different implementations can be devised so that the transistor can be operated in constant current or constant Gm operation.
There are no restrictions on the class of operation of the RF circuit.
“Tracking bias” circuits can be made to keep different device parameters constant regardless of process variations, temperature changes, etc. Of course, no circuit can keep all parameters of a transistor constant. These circuits work by varying the bias (generally the gate voltage) on the RF transistor in proportion with one parameter so that variations in another parameter are cancelled out. Generally, designers aim to keep either the transconductance (Gm) or the drain current (Id) constant, or to keep the drain current at a fixed proportion of the saturated drain current (Idss). Keeping these DC parameters constant is sufficient to ensure that RF parameters are also held constant.
An existing “tracking bias” circuit biases the transistor at a constant fraction of the saturated drain current (Idss), and is simpler and less expensive to manufacture. Unfortunately, the circuit is not sensitive to changes in pinchoff voltage, causing excessive current to be drawn for more negative pinchoff voltages and insufficient current to be drawn for more positive pinchoff voltages. In the former case, this causes a decrease in the efficiency of the controlled RF transistor. In the latter case, this causes premature saturation or “clipping” of the input signal.
Another known “tracking bias” circuit biases the transistor at approximately a constant absolute current. Unfortunately, this technique is limited in its range of IS applicability. Specifically, it is limited to RF transistors that have a pinchoff voltage of less than 0.7 volts. The reference transistor operates at a lower current that the RF transistor, so tracking between the reference transistor and the RF transistor may be poor.
The background information provided above clearly indicates that there exists a need in the industry to provide an improved bias circuit for depletion mode field-effect transistors, in order to achieve maximum efficiency of operation.
SUMMARY OF THE INVENTION
The present invention provides a bias circuit for biasing a depletion mode power transistor. The bias circuit includes a voltage offset circuit, a transistor, first and second resistors and first and second power supply connections. A voltage differential may be impressed across the power supply connections in order to energize the bias circuit. The voltage offset circuit has an input and an output, the input being connected to the drain terminal of the transistor and the output to the gate terminal of the depletion mode power transistor. The gate terminal of the transistor is coupled to the first power supply connection. The source terminal of the transistor is also coupled to the first power supply connection, through the first resistor. The drain terminal of the transistor is coupled to the second power supply, through the second resistor. The bias circuit is capable of generating a bias voltage that, when applied to the gate terminal of the power transistor, maintains a is substantially constant drain current through the power transistor.
The voltage offset circuit applies a DC voltage shift to an electrical signal received at the input of the voltage offset circuit.
In this specification, the terms “connected” and “coupled” are equivalent to “in an electrical pathway”, where the electrical pathway may or may not include other electrical components, such as resistors, inductors and capacitors, among other possibilities.
Specifically, the improvement in the bias circuit arises from the topology of the bias circuit, whereby the voltage offset circuit is coupled between the drain terminal of the transistor of the bias circuit and the gate terminal of the power transistor. This topology ensures that the transistor of the bias circuit is operating at approximately the same fraction of IDSS of the transistor (the maximum current through the transistor channel) as the biased power transistor. Thus, the bias circuit and the biased power transistor are operating over similar regimes, allowing them to track more efficiently over process variations,
In a specific example of implementation, the voltage offset circuit is formed primarily of a diode, connected at its anode to the gate terminal of the power transistor and at its cathode to the drain terminal of the transistor of the bias circuit. The voltage of

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