Bias circuit for depletion mode field effect transistors

Details Bias circuit for depletion mode field effect transistors Bias circuit for depletion mode field effect transistors

1995-04-10

1996-04-09

Mottola, Steven J.

Amplifiers

With semiconductor amplifying device

Including field effect transistor

330289, 330296, H03F 316

Patent

active

055065449

ABSTRACT:
An amplifier (10) receives a bias voltage to the gate of a depletion mode field effect transistor (12). In one embodiment, a bias circuit (20) offsets (22) the bias voltage from a power supply potential (26) to maintain substantially constant drain current over a range of threshold voltages (34,36,38) caused by process and temperature variation. In an alternate embodiment, a transistor (58) in the bias circuit (50) provides an incremental current flow to compensate the bias voltage of the MESFET for variation in threshold voltages. The bias circuit is applicable to other depletion mode field effect transistor circuits having a negative threshold voltage.

REFERENCES:
patent: 5068623 (1991-11-01), Camin et al.
patent: 5361007 (1994-11-01), Ohta

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