Bias circuit for class AB high frequency amplifiers

Details Bias circuit for class AB high frequency amplifiers Bias circuit for class AB high frequency amplifiers

2001-10-19

2003-09-02

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

C330S267000, C330S311000

Reexamination Certificate

active

06614306

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and apparatus for biasing high-speed class AB amplifiers. More specifically, the present invention is directed to improving the frequency response of a class AB amplifier stage by properly arranging a diode multiplier circuit that is in the bias stage of the amplifier.
BACKGROUND OF THE INVENTION
A diode multiplier includes a transistor and a resistor network. The transistor has an inherent base-emitter voltage (V
BE
). The resistor network in the diode multiplier is arranged such that an output voltage that corresponds to a multiplication of the base-emitter voltage is provided. The diode multiplier ideally maintains an output voltage that is constant. In practice, the output voltage increases as the collector current of the transistor in the diode multiplier increases.
A conventional diode multiplier may be arranged in a cascode amplifier. As the input signal to the amplifier increases, the collector current of the transistor in the diode multiplier increases. A large transistor, or a Darlington device, can be used to minimize the increase in the collector current of the transistor in the diode multiplier. The use of such large devices results in a corresponding increase in the parasitic collector capacitance of the device in the diode multiplier. The increase of the capacitance causes an increase in the RC time constant (formed by a load resistance and the collector capacitance, among others). Conventional diode multipliers have poor frequency response characteristics due to the collector capacitance.
The transistor in the diode multiplier is sized to bias the complementary inputs of a class AB amplifier. The bias current provided for the class A stage of the class AB amplifier must be high when the amplifier is operating near the supply rail. However, the bias currents should be limited to minimize excessive bias currents at low voltage outputs of the amplifier. Excessive bias currents for low voltage outputs of the amplifier can result in “shoot through” of the class B stage of the class AB amplifier. “Shoot through” may result in excessive power dissipation and possibly thermal runaway. The bias current provided by the diode multiplier must also be sufficiently low for when the amplifier is operating near the supply rail, but not so low as to provide insufficient bias current at low voltage outputs of the amplifier. An insufficient bias current at low voltage can result in “crossover distortion” of the class A stage of the class AB amplifier.
SUMMARY OF THE INVENTION
The present invention relates to a method and apparatus for biasing high-speed class AB amplifiers. More specifically, the present invention is directed to improving the frequency response and reducing the power consumption of a class AB amplifier stage by arranging a diode multiplier circuit in the bias stage of the amplifier.
A high-speed amplifier according to the present invention includes a cascode input stage for receiving an input voltage, a diode multiplier for providing a temperature-compensated bias current, and a class AB amplifier stage for providing an output signal. The cascode input stage sinks a cascode current in proportion to an input signal. The cascode current is sourced in part through a first load resistor that limits a current through the transistor of the diode multiplier. The cascode current is also sourced in part through a second load resistor that sources a majority of the cascode current. Accordingly, the diode multiplier transistor may be made smaller than the cascode transistor of the cascode input stage because the transistor of the diode multiplier carries less current than a transistor in the cascode input stage. The reduction in size of the diode multiplier transistor enhances the frequency response of the diode multiplier. Any rise in voltage in the diode multiplier transistor V
CE
is applied to a resistor network that increases the bias current of the diode multiplier transistor, which negates the rise of the diode multiplier transistor V
CE
and maintains the V
CE
at a stable level. The diode multiplier provides a temperature-compensated bias current to the class AB amplifier stage for producing the output signal.


REFERENCES:
patent: 5337012 (1994-08-01), Dijkmans
patent: 6163211 (2000-12-01), Morrish
patent: 6417736 (2002-07-01), Lewyn

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