Bias circuit for a transistor of a storage cell

Details Bias circuit for a transistor of a storage cell Bias circuit for a transistor of a storage cell

2001-06-29

2003-08-12

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06605982

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to integrated circuits and, in particular, to a bias circuit for a programmable storage cell that utilizes a floating-gate transistor as a storage unit.
2. Description of Related Art
Read-only memories are commonly organized in matrix form, utilizing rows and columns. The rows are referred to as bit rows, and the columns are referred to as word columns. Each intersection of a row and column forms a storage cell whose electrical state represents an information element. Depending on the technology used, these storage cells are programmable one or more times, and they can be erased individually or comprehensively.
The rows and the columns of the memories are generally tested following production to ensure that access can be made to all the storage cells of the memories and that each cell can be programmed and erased in such a way that there is definite knowledge, at any time, of the electrical state of the storage cells.
A programmable memory circuit typically comprises a floating-gate transistor, commonly called a fuse, that is series-connected with a current source. Each floating-gate transistor represents one address bit. Depending on the electrical state of the floating-gate transistor (i.e., whether there are electrons present at its gate), the fuse behaves like an open circuit or like a resistor. If it behaves like a resistor, it may conduct current. On the contrary, if it behaves like an open circuit, it can not conduct current. A current detector may then be used to read the data stored therein by detecting the currents flowing at each fuse.
Reference is now made to
FIG. 1
wherein there is shown an integrated circuit
1
in accordance with U.S. Pat. No. 5,900,756. The circuit
1
includes a plurality of storage circuits
2
(not all of which are represented). Each storage circuit
2
includes a cell referred to as a fuse. More specifically, the fuse is a floating-gate transistor
3
that is series connected with an N type isolation transistor
4
between a reference terminal
5
and a supply terminal
6
. Typically, the reference terminal
5
gives a ground potential GND and the supply terminal
6
gives a positive supply potential VCC of the order of some volts (for example, five volts).
The floating-gate transistor
3
is connected through its control gate, by means of a circuit (not explicitly shown), to either the ground potential GND or the supply potential VCC. The source of transistor
3
is connected to the ground terminal
5
and the drain of transistor
3
is connected to the source of the isolation transistor
4
. The isolation transistor
4
has its drain connected through a resistor
25
to the supply terminal
6
.
A programming and reading circuit
7
is connected to the drain of the floating-gate transistor
3
and is also connected to the drain of the isolation transistor
4
. In a first mode of operation referred to as a “programming mode,” the circuit applies a voltage of some volts to the floating-gate transistor
3
, with the control gate of this transistor
3
being connected to ground. In a second mode of operation referred to as a “reading mode,” the circuit
7
detects a possible passage of current through resistor
25
and hence into the floating-gate transistor
3
. This passage of current depends on the electrical state of the floating-gate transistor
3
(namely the presence or non-presence of electrons on the floating gate),.
More specifically, the circuit
2
operates in the following manner:
in programming mode, depending on the electrical state desired, a high value (for example, 10 volts) is applied (or not applied) on the drain of the floating-gate transistor in order to inject (or not inject) electrons into the floating gate, the control gate of the floating gate transistor is connected to ground, and the control gate of the isolation transistor is also connected to ground; and
in reading mode (i.e., current passage detection to read the addressed bit), the N type isolation transistor is biased positively at its control gate in order to be turned on, and the control gate of the floating-gate transistor is connected to a positive supply potential VCC given by the supply terminal.
When configured in the reading mode, the isolation transistor is on and a current may flow, as the case may be, depending on the electrical state of the floating-gate transistor. The isolation transistor is used to impose a constant voltage on the drain of the floating-gate transistor to have the same reading conditions whatever the current given by the supply terminal. In this case, the current read is only a function of the threshold voltage of the floating-gate transistor, and this threshold voltage varies according to the electrical state of this transistor.
To impose a constant voltage on the drain of the floating-gate transistor, a constant bias voltage is imposed on the isolation transistor. This bias voltage is typically twice the threshold voltage Vt of the isolation transistor (wherein typically Vt is approximately one volt). A low bias voltage is chosen in order to limit the current produced and hence the consumption of the circuit.
A bias circuit, capable of giving adequate voltage in programming mode (for the connection to the ground of the control gate of the isolation transistors), is accordingly needed to operate the circuit
2
. Irrespective of the mode of operation in effect, the bias circuit must provide the proper bias voltage. This is the case, for example, in a watch mode of operation wherein the memory is supplied with bias but is not currently being used for reading or writing. It is preferable that the bias circuit operate as quickly as possible during the activation of the memory (for example, when reading and writing).
The integrated circuit
1
accordingly includes a first bias circuit
8
having a control terminal
10
and an output terminal
11
. The first bias circuit
8
is formed by two arms, each arm consisting of series-connected transistors between the supply terminal
6
and the ground terminal
5
. A first arm
12
has a P type transistor
14
a
whose source is connected to the supply terminal
6
and whose drain is connected to the drain of an N type transistor
15
a
.The source of the N type transistor
15
a
is connected to the drain and to the control gate of an N type transistor
16
a
, configured as a diode, with the source of transistor
16
a
being connected to the ground terminal
5
. The second arm
13
of the first bias circuit
8
similarly includes a P type transistor
14
b
whose source is connected to the supply terminal
6
and whose drain is connected to the drain of an N type transistor
15
b
. The source of this N type transistor
15
b
is connected to the drain and to the control gate of an N type transistor
17
, configured as a diode. The source of the transistor
17
is connected to the drain and to the control gate of an N type transistor
16
b
, also configured as a diode, with the source of transistor
16
b
being connected to the ground terminal
5
. The control gates of the P type transistors
14
a
and
14
b
are connected to each other and to the control terminal
10
. The control gate of the N type transistor
15
b
of the second arm
13
is connected to the drain of the P type transistor
14
a
of the first arm
12
. The control gate of the N type transistor
15
a
of the first arm
12
is connected to the source of the N type transistor
15
b
of the second arm
13
. The source of transistor
15
b
is further connected to the output terminal
11
. The first bias circuit
8
further includes an N type transistor
18
mounted at the output between the output terminal
11
and the ground terminal
5
. This output N type transistor
18
has its control gate connected to the control terminal
10
.
A brief description of the operation of the first bias circuit
8
will now be provided. The control terminal
10
receives a first binary control signal VB
0
. The output terminal
11
supplies a binary bias

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