Bias circuit for a subranging analog to digital converter

Details Bias circuit for a subranging analog to digital converter Bias circuit for a subranging analog to digital converter

1989-12-07

1991-05-28

Pellinen, A. D.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

323312, 341118, H03M 114

Patent

active

050198211

ABSTRACT:
Through first and second external terminals, fixed potentials are applied to both ends of a first ladder resistor network. A second ladder resistor network is connected at one end to a second transistor. The first external terminal is connected to a first transistor through a resistor, the resistor and the resistors of the first and second ladder resistor networks being of the same kind. A positive input terminal of an operational amplifier is connected to a node between the resistor and the first transistor. A negative input terminal of the amplifier receiving a reference voltage is connected to the second external terminal. The first and second transistors are driven by the output signal of the amplifier. The amplifier cooperates with the first transistor such that a potential at the node is equal to the potential of the reference voltage. As a result, a current flowing through the resistor is proportional to a current flowing through the first ladder resistor network. Since the current, which is based on the operation of the second transistor, flows into the second ladder resistor network, the current flowing through the first transistor is proportional to a current flowing through the second ladder resistor network.

REFERENCES:
patent: 4680535 (1987-07-01), Talmor
patent: 4745393 (1988-05-01), Tsukada et al.
patent: 4808907 (1989-02-01), Main
Technical Report of the Electronic Information Communication Society of Japan, pp. 13-17, "Two Step Parallel ADC with Peripheral Analog and Digital Circuit" (Sep. 1987).

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