Bias circuit for a memory line decoder driver of nonvolatile mem

Details Bias circuit for a memory line decoder driver of nonvolatile mem Bias circuit for a memory line decoder driver of nonvolatile mem

1994-12-02

1996-03-12

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, 36518909, G11C 800

Patent

active

054992176

ABSTRACT:
A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage alternatively connects the gate terminal of the pull-up transistor to a capacitor, with which the charge is distributed, and to the supply.

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