Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2011-04-05
2011-04-05
Mottola, Steven J (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
Reexamination Certificate
active
07920028
ABSTRACT:
A bias circuit for applying a bias voltage to a nonlinear amplification circuit, including a constant-current source; and a first, second, third, and fourth transistors, wherein a current mirror circuit is configured by the first transistor and the second transistor, and the bias voltage is outputted from the drain of the second transistor, gate lengths and gate widths of the first and second transistor are the same, gate lengths of the first to fourth transistor are the same, and gate lengths and gate widths of the first, second, third, and fourth transistor are configured so that k4−0.5−k3−0.5is approximately 1, where k3stands for a ratio of a gate width of the third transistor to the gate width of the first transistor and k4stands for a ratio of a gate width of the fourth transistor to the gate width of the first transistor.
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Arai Tomoyuki
Kudo Masahiro
Fujitsu Limited
Katten Muchin & Rosenman LLP
Mottola Steven J
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