Bias circuit

Details Bias circuit Bias circuit

2011-03-15

2011-03-15

Berhane, Adolf (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000

Reexamination Certificate

active

07906954

ABSTRACT:
A control circuit U1comprises four PMOS transistors MP1-MP4and receives a voltage Vn and a voltage Vss. MP1and MP3, and, MP2and MP4are respectively connected in series between power supply Vdd and a fixed voltage Vss. Gate terminal of MP2is connected to Vss. Reference current and its copy current F1respectively flow through NMOS transistors M1and M2, of which respective source terminals are connected to Vss. Gate width of M2is a quarter of that of M1. Drain terminal is connected to the gate terminals of MP1and MP2. Node between source terminal of MP2and drain terminal of MP3is connected to gate terminal of MP1, and node between source terminal of MP2and drain terminal of MP4is connected to gate terminal of MP2. The control circuit U1controls gate terminal voltage of M1to make an overdrive voltage of M1becomes Vn.

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“Extended European Search Report”, mailed by EPO and corresponding to European patent application No. 05 78 8272.2 on Sep. 29, 2010.

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