Bi-phase decoder phase-lock loop in CMOS

Details Bi-phase decoder phase-lock loop in CMOS Bi-phase decoder phase-lock loop in CMOS

1990-10-11

1994-01-04

Chin, Stephen

Pulse or digital communications

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375119, 331 1A, H03D 324

Patent

active

052767167

ABSTRACT:
A bi-phase decoder for extraction of an embedded clock in a Manchester encoded signal operating at about ten megahertz. A phase-lock loop (PLL) includes a phase frequency detector and an interruptible voltage controlled oscillator (VCO). The PLL has a narrow bandwidth for stability to reduce effects of five megahertz components on clock extraction. The bi-phase decoder has a fast acquisition time to ensure frequency and phase lock during a preamble portion of an input data packet. A clock reference operates the PLL and the VCO at a nominal frequency of the embedded clock. Receipt of a data packet initiates interruption of the VCO operation to switch in the received data. The VCO resumes operation in phase with the received data packet and at about the proper frequency, therefore acquisition is fast. The VCO is designed to resume operation after operation at a particular phase to help in phase alignment.

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Gardner, F. M., "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, vol. Com-28, No. 11, pp. 1849-1858 (Nov. 1980).

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