Bi-MOS logic circuit having a totem pole type output buffer sect

Details Bi-MOS logic circuit having a totem pole type output buffer sect Bi-MOS logic circuit having a totem pole type output buffer sect

1988-02-01

1989-07-04

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307570, H03K 1901

Patent

active

048453862

ABSTRACT:
A totem pole type output buffer section comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. These NPN bipolar transistors are selectively switch-controlled by a first MOS FET. Another NPN bipolar transistor is darlington-connected to the pull-down NPN bipolar transistor, and is switch-controlled by the second MOS FET. The second MOS FET is of the same conductivity type as and has a gate connected to a gate of the first MOS FET.

REFERENCES:
patent: 3879619 (1975-04-01), Pleshko
patent: 4649294 (1987-03-01), McLaughlin
patent: 4661723 (1987-04-01), Masuda et al.
patent: 4678940 (1987-07-01), Vasseghi et al.
patent: 4678943 (1987-07-01), Uragami et al.
patent: 4697103 (1987-09-01), Ferris et al.
patent: 4733110 (1988-03-01), Hara et al.
Lin et al., "Complementary MOS-Bipolar Transistor Structure", IEEE T.E.L.D., vol. ED-16, No. 11, Nov. 1969, pp. 945-951.

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