Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-01-30
1991-05-21
Hudspeth, David
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307481, 307570, 3072722, H03K 1901
Patent
active
050178083
ABSTRACT:
Disclosed herein is a Bi-MOS logic circuit comprising first and second NPN transistors forming an output buffer; first and second MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-latching mode; and third and fourth MOS transistors for controlling the NPN transistors when the logic circuit is set to a data-inputting mode. The Bi-MOS logic circuit further comprises a switch circuit for discharging a parasitic capacitor located at the node of the series circuit comprised of the first and second MOS transistors.
REFERENCES:
patent: 4719373 (1988-01-01), Masuda et al.
patent: 4804869 (1989-02-01), Masuda et al.
patent: 4841172 (1989-06-01), Ueno et al.
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 4880998 (1989-11-01), Ueda
patent: 4902914 (1990-02-01), Masuoka
patent: 4914318 (1990-04-01), Allen
"BiCMOS LSSD Latch in Integrated Complementary Logic", IBM T.D.B., vol. 32, No. 53, Oct. 1989, pp. 285-286.
CMOS Multi-Way and Logic, IBM Technical Disclosure Bulletin, vol. 28, No. 12, p. 5317, New York (May 1986).
Ofusa Kumi
Ueno Masaji
Hudspeth David
Kabushiki Kaisha Toshiba
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