Bi-MOS levelshift circuit capable of controlling power consumpti

Details Bi-MOS levelshift circuit capable of controlling power consumpti Bi-MOS levelshift circuit capable of controlling power consumpti

1987-12-17

1989-08-22

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307450, 307451, 307570, 307 238, H03K 1756

Patent

active

048598780

ABSTRACT:
Disclosed is a levelshift circuit comprising a P-channel MOS transistor wherein the source is connected to a high power potential in a low-voltage power circuit, a first N-channel double-diffused field effect transistor wherein the source is connected to a ground potential and the gate and drain are shorted with each other and connected to the drain of the P-channel MOS transistor, a second N-channel double-diffused field effect transistor wherein the structure is the same as that of the first N-channel double-diffused field effect transistor or different only in its gate width at a predetermined ratio from that of the first N-channel double-diffused field effect transistor, the source is connected to the ground potential and the gate is connected to the gate and drain of the second N-channel double-diffused field effect transistor, a PNP transistor wherein the emitter is connected to the high power potential in the high-voltage power circuit, the base is connected to the drain of the second N-channel double-diffused transistor and the collector is connected to a load, and a switch whereby the gate and drain of the first N-channel double-diffused field effect transistor is short-circuited or opened with respect to the ground potential.

REFERENCES:
patent: 4609929 (1986-09-01), Jayaraman et al.
patent: 4639761 (1987-01-01), Singer et al.
patent: 4701642 (1987-10-01), Pricer
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4760293 (1988-07-01), Hebenstreit
Chang et al., "High-Voltage FET Integrated Circuit Process", IBM T. D. B., vol. 16, No. 5, Oct. 1973, pp. 1635-6.

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