Bi-MOS circuit capable of high speed operation with low power co

Details Bi-MOS circuit capable of high speed operation with low power co Bi-MOS circuit capable of high speed operation with low power co

1988-08-17

1990-05-15

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307570, 307270, H03K 1704

Patent

active

049260693

ABSTRACT:
A Bi-MOS circuit includes an input terminal, an output terminal, an N-channel MOS transistor having a gate connected to the input terminal, a source connected to the ground and a drain, an NPN bipolar transistor having a collector connected to a first power voltage line, an emitter connected to the output terminal and a base connected to a drain of the N-channel MOS transistor, a load element connected between the base of the NPN bipolar transistor and a second power voltage line lower than the first power voltage line and a switching element connected between the output terminal and the ground and having a control electrode connected to the input terminal, the switching element connecting the output terminal and the ground when a first level of input signal turning the N-channel MOS transistor on is inputted to the input terminal and disconnecting the output terminal from the ground when a second level of the input signal turning the N-channel MOS transistor off is inputted to the input terminal.

REFERENCES:
patent: 4558234 (1985-12-01), Suzuki et al.
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4804868 (1989-02-01), Masuda et al.
patent: 4808850 (1989-02-01), Masuda et al.
patent: 4816705 (1989-03-01), Ohba et al.
"NEC Research and Development", No. 84, Jan. (1987), pp. 127-130.
"VLSI Design", Aug. (1984), pp. 98-100.
"IEEE International Conference on Computer Design: VLSI in Computers", IEEE Catalog No. 84CH 2080-0, pp. 428-433.

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