Bi-level pulse accumulator

Details Bi-level pulse accumulator Bi-level pulse accumulator

1992-09-08

1994-04-19

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

377 20, 328111, 307234, H03K 526

Patent

active

053048555

ABSTRACT:
A pulse accumulator (24) operates in a pulse measurement mode. In the pulse measurement mode, accumulator (24) measured pulse lengths of consecutive high and low input signal pulses in reference to a clock signal. A leading-edge capture circuit (50) asserts a leading-edge pulse to indicate a rising edge of the input signal and a trailing-edge capture circuit (52) asserts a trailing-edge pulse to indicate a falling edge of the input signal. The leading-edge and trailing-edge pulses are logically combined (70) to provide a load signal to enable counter (76) to provide an accumulate value to a buffer register (78). After a predetermined delay (62, 64), each of the leading-edge and trailing-edge pulses are logically combined (66) to provide a clear signal which indicates the input signal has transitioned and counter (76) should be cleared to begin measuring a length of a next pulse.

REFERENCES:
patent: 3555434 (1971-01-01), Sheen
patent: 3996586 (1976-12-01), Dillon et al.
patent: 4511846 (1985-04-01), Nagy et al.
patent: 4730131 (1988-03-01), Sauer
patent: 4904947 (1990-02-01), Olivenbaum et al.
patent: 5223742 (1993-06-01), Schumacher
"Microprocessor, Microcontroller and Peripheral Data"-vol. 1, published by Motorola, Inc. in 1988, pp. 3-859 through 3-898.
"HC11: M68HC11 Reference Manual" published by Motorola, Inc. in 1988, pp. 11-1 thorugh 11-12.

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