Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-08-05
2004-02-24
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S907000, C365S063000
Reexamination Certificate
active
06696762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits (ICs). Particularly, there is a RAM device where digit and digit bar, defined as a pair, are laid out vertically (in the z-axis) to each other, whereas the pairs of digit lines are laid out to be parallel (in the x or y axis) to each other. Additionally, the vertically aligned digit line pairs allow usage of memory cells having a six square feature area (6F
2
) or less, where F is defined as the minimum realizable photolithographic process dimension feature size.
2. State of the Art
Dynamic random access memory (DRAM) production in the early days resulted in large chips. Manufacturing of these chips, at first, was not concerned with shrinking every part down to its smallest size. At this time the open memory array was the standard design: true digit lines on one side and complement digit (also known as digit bar or digit*) lines on the opposite side, with sense amps in the middle. However, once the DRAMS reached the 256K memory density, shrinking of all features became important.
However, to push to even higher densities, like a one Megabit density, the open architecture proved to be inadequate because of the poorer signal to noise problem. As a result, the folded bit line architecture was developed. Yet, to use this architecture, the original memory cell from the open architecture could not be used. Thus, new cells were designed. There resulted a memory cell with a minimum size of eight square feature area (8F
2
). The folded architecture eliminated the signal to noise problems. Thus, further shrinkage of the other components on the DRAM resulted in an overall smaller DRAM package.
Problem
For some time now, there have been many ways developed to shrink the die size. However, a new shrinkage barrier has been reached as designs approach densities of 16 and 64 Meg chips. Every aspect of the die now has to be designed with minimal size. Thus, it is now necessary to shrink the previously acceptable eight square feature area (8F
2
) cells. Cell sizes of six square feature area (6F
2
) to four square feature area (4F
2
) are now needed. As a result, customers now need memory cells of six square feature area (6F
2
) or smaller that will also avoid the previous signal to noise ratio problems.
Note, the above described problem, as well as other problems, is solved through the subject invention and will become more apparent, to one skilled in the art, from the detailed description of the subject invention.
BRIEF SUMMARY OF THE INVENTION
One skilled in the art will appreciate the advantage of the bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F
2
) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lay on top of each other like a double decker overpass road. Additionally, this design allows routing of digit lines on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.
To achieve the digit line switching, several modes of vertical twisting were developed. For a given section of the array, the twists are alternated between adjacent digit line pairs such that the overall twist resembles the traditional folded digit line twist. This twisting of the lines ensures that the signal to noise ratio of the bi-level digit line architecture can be as good as or may be even better than the folded digit line.
Other features and advantages of the present invention may become more clear from the following detailed description of the invention, taken in conjunction with the accompanying drawings and claims, or may be learned by the practice of the invention.
REFERENCES:
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4914502 (1990-04-01), Lebowitz et al.
patent: 4922460 (1990-05-01), Furutani et al.
patent: 4967396 (1990-10-01), Kajigaya et al.
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5014110 (1991-05-01), Satoh
patent: 5107459 (1992-04-01), Chu et al.
patent: 5138412 (1992-08-01), Hieda et al.
patent: 5170243 (1992-12-01), Dhong et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5208180 (1993-05-01), Gonzalez
patent: 5243558 (1993-09-01), Saeki
patent: 5280443 (1994-01-01), Hidaka et al.
patent: 5315542 (1994-05-01), Melzner
patent: 5396450 (1995-03-01), Takashima et al.
patent: 5396451 (1995-03-01), Ema
patent: 5499205 (1996-03-01), Ahn et al.
patent: 5534732 (1996-07-01), DeBrosse et al.
patent: 5581126 (1996-12-01), Moench
patent: 5625234 (1997-04-01), Suzuki et al.
patent: 5670815 (1997-09-01), Childs et al.
patent: 5680347 (1997-10-01), Takeuchi et al.
patent: 5815428 (1998-09-01), Tsuruda et al.
patent: 5838038 (1998-11-01), Takashima et al.
patent: 5864181 (1999-01-01), Keeth
patent: 5877976 (1999-03-01), Lattimore et al.
patent: 5940321 (1999-08-01), Takeuchi et al.
patent: 5949698 (1999-09-01), Shirley
patent: 6005265 (1999-12-01), Kuroda
patent: 6018172 (2000-01-01), Hidaka et al.
patent: 6034879 (2000-03-01), Min et al.
patent: 6043562 (2000-03-01), Keeth
patent: 6084307 (2000-07-01), Keeth
patent: 6094370 (2000-07-01), Takashima
patent: 6185123 (2001-02-01), Allen et al.
patent: 6188598 (2001-02-01), Mueller et al.
patent: 6222275 (2001-04-01), Keeth
patent: 6243311 (2001-06-01), Keeth
patent: 6259621 (2001-07-01), Li et al.
patent: 6429529 (2002-08-01), Keeth
patent: 6504255 (2003-01-01), Keeth
patent: 4433695 (1995-03-01), None
patent: 0078338 (1983-05-01), None
patent: 60-258795 (1984-12-01), None
patent: 3-174765 (1991-07-01), None
Ahn et al., “Bidirectional Matched Global Bit Line Scheme for High Density DRAMS”, (Abstract), pps.91-92. No date available.
Hamada et al., “A Split -Level Diagonal Bit-Line (SLDB) Stacked Capacitor Cell for 256MbDRAMs”, IEEE, Apr.; 1992, pps. 799-802.
Hidaka et al., “A Divided/Shared Bit-Line Sensing Scheme for ULSI DRAM Cores”, Journal of Solid-State Circuit, vol. 26, No. 4, Apr. 1991, pp. 473-477.
IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, pps. 1314-1315.
IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, pps. 246-248.
Inoue et al., “A 16Mb DRAM with An Open Bit-Line Architecture”, International Solid State Circuits Conference, IEEE, 1988, pp. 246-247.
Kimura et al., “A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture”, Nov. 11, 1991, IEEE, Journal of Solid-State Circuit, pps. 1511-1518.
Takashima et al., “Open/Folded Bit-Line Arrangement for Ultra High-Density DRAMs”, (Abstract), pps. 89-90. No date available.
Micro)n Technology, Inc.
TraskBritt
Wilson Allan R.
LandOfFree
Bi-level digit line architecture for high density DRAMS does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bi-level digit line architecture for high density DRAMS, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bi-level digit line architecture for high density DRAMS will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3283519