Bi-level digit line architecture for high density DRAMs

Details Bi-level digit line architecture for high density DRAMs Bi-level digit line architecture for high density DRAMs

1997-10-15

1999-01-26

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257907, 257908, 365 69, 365210, H01L 2348

Patent

active

058641815

ABSTRACT:
There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for 6F**2 cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

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