Bi-directional silicon controlled rectifier for...

Details Bi-directional silicon controlled rectifier for... Bi-directional silicon controlled rectifier for...

2005-01-04

2005-01-04

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Bidirectional rectifier with control electrode

C257S119000, C257S122000, C257S173000, C257S396000

Reexamination Certificate

active

06838707

ABSTRACT:
A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.

REFERENCES:
patent: 4939616 (1990-07-01), Rountree
patent: 5012317 (1991-04-01), Rountre
patent: 5150187 (1992-09-01), Huang
patent: 5225702 (1993-07-01), Chatterjee
patent: 5453384 (1995-09-01), Chatterjee
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5502328 (1996-03-01), Chen et al.
patent: 5519242 (1996-05-01), Avery
patent: 5572394 (1996-11-01), Ker et al.
patent: 5581104 (1996-12-01), Lowrey et al.
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5631793 (1997-05-01), Ker et al.
patent: 5646808 (1997-07-01), Nakayama
patent: 5654862 (1997-08-01), Worley et al.
patent: 5719737 (1998-02-01), Maloney
patent: 5754381 (1998-05-01), Ker
patent: 5807791 (1998-09-01), Bertin et al.
patent: 5811857 (1998-09-01), Assaderaghi et al.
patent: 5903420 (1999-05-01), Ham
patent: 5907462 (1999-05-01), Chatterjee et al.
patent: 5910874 (1999-06-01), Iniewski et al.
patent: 5932918 (1999-08-01), Krakauer
patent: 5940258 (1999-08-01), Duvvury
patent: 5990520 (1999-11-01), Noorlag et al.
patent: 6015992 (2000-01-01), Chatterjee et al.
patent: 6034397 (2000-03-01), Voldman
patent: 6081002 (2000-06-01), Amerasekera et al.
patent: 6258634 (2001-07-01), Wang et al.
S.Voldman, et al., “Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined and Polysilicon- Bound Source/Drain Diodes for ESD Networks,” in Proc. of EOS/ESD Symp., 1988, pp. 151-160.
S. Voldman, et al., “Analysis of Snubber-Clamped Diode-String Mixed Voltage Interface ESD Protection Network for Advanced Microprocessors,” in Proc. of EOS/ESD symposium, 1995, pp. 43-61.
M. J. Pelgrom, et al., “A 3/5 V Compatible I/O Buffer,” IEEE Journal of Solid-State Circuits, vol. 30, No. 7, pp. 823-825, Jul. 1995.
G.P. Singh, et al., “High-Voltage-Tolerant I/OBuffers with Low-Voltage CMOS Process,” IEEE Journal of Solid-State Circuits, vol. 34, No. 11, pp. 1512-1525, Nov. 1999.
H. Sanchez, et al., A Versatile 3.3/2.5/1.8-V CMOS I/O Driver Built in 02. -μm, 3.5-nm Tox, 1.8 -V CMOS Technology, IEEE Journal of Solid-State Circuits, vol. 34, No. 11.pp. 1501-1511, Nov. 1999.
C. Richier, P. Salome, G. Mabboux, I. Zaza, A. Juge, and P. Mortin, Investigation on Different ESD Protection Strategies Devoted to 3.3V RF Applications (2 (GHz) in a 0.18 μm CMOS Process, in Proc. of EOS/ESD Symp., 200, pp. 251-259.
T.-Y. Chen and M.-D. Ker, “Design on ESD Protection Circuit With Low and Constant Input Capacitance,”in Proc. of IEEE Int. Symp. on Quality Electronic Design, 2001, pp. 247-247.
M.-D. Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang, ESD Protection Design on Analog Pin With Very Low Input Capacitance for RF or Current-Mode Applications,IEEE Journal of Solid-State Circuits, vol. 35, pp. 1194-1199, 2000.
N. K. Verghese and D. Allstot, “Verification of RF and Mixed-Signed Integrated Circuits for Substrate Coupling Effects”, inProc. of IEEE Custom Integrated Circuits Conf:, 1997, pp. 363-370.
M.Xu, D. Su, D. Shaeffer, T.Lee, and B. Wooley, Measuring and Modeling the Effects of Substrate Noise on LNA for a CMOS GPS Receiver,IEEE Journal of Solid-State Circuits, vol. 36, pp. 473-485, 2001.
R. Gharpurey, “A Methodology for Measurement and Characterization of Substrate Noise in High Frequency Circuits”, inProc. of IEEE Custom Integrated Circuits Conf., 1999, pp. 487-490.
M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, PhysicalDesign Guides for Substate Noise Reduction in CMOS Digital Circuits,IEEE Journal of Solid-State Circuits, vol. 36, pp. 539-549, 2001.
M.-D. Ker, T-Y, Chen, C-Y. Wu, and H.-H. Chang, ESD Protection Design on Analog Pin WIth Very Low Input Capacitance for High-Frequency or Current-Mode Applications,IEEE Journal of Solid-State Circuits, vol. 35, pp. 1194-1199, 2000.
M.-D. Ker, Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuit for Submicron CMOS VLSI,IEEE Trans. on Electron Devices, vol. 46, pp. 173-183, 1999.
M.-D. Ker, et al., “CMOS On-Chip ESD Protection Design with Substrate-triggering Technique,” Proc. of ICECS, vol. 1, pp. 273-276, 1998.
C. Duvvury et al., “Dynamic Gate Coupling for NMOS for Efficient Output ESD Protection”, Proc. of IRPS, pp. 141-150, 1992.

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