Bi-directional serializer/deserializer with discretionary...

Details Bi-directional serializer/deserializer with discretionary... Bi-directional serializer/deserializer with discretionary...

2006-09-19

2006-09-19

Pham, Brenda (Department: 2664)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S541000

Reexamination Certificate

active

07110424

ABSTRACT:
A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r≧s.

REFERENCES:
patent: 6097210 (2000-08-01), Iwanczuk
patent: RE37401 (2001-10-01), Yamashita
patent: 6430201 (2002-08-01), Azizoglu et al.
patent: 2003/0031133 (2003-02-01), Momtaz

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