Bi-directional scan design with memory and latching circuitry

Details Bi-directional scan design with memory and latching circuitry Bi-directional scan design with memory and latching circuitry

1995-02-28

1998-01-06

Beausoliel, Jr., Robert W.

Excavating

G01R 3128

Patent

active

057062960

ABSTRACT:
A scan cell (51) for use at an input/output terminal includes memory circuitry (Mem 1) for storing test data from a test data path, and a latching circuit (S4, LOB; S6, LIB) connected to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry. The input/output terminal has an input buffer (IB) and an output buffer (3SOB) associated therewith, and the latching circuit includes one of the input buffer and the output buffer.

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