Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2003-05-29
2004-11-09
Phan, Trong (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S063000, C365S203000, C365S207000
Reexamination Certificate
active
06816397
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit memories, and more particularly to a system and method, in a semiconductor integrated circuit memory, of transferring read and write data signals on a bi-directional primary data line between primary sense amplifiers and secondary sense amplifiers.
BACKGROUND OF THE INVENTION
In a typical integrated circuit memory, the maximum speed of memory access from outside the memory is determined by the performance of the memory array. The speed of access in reading data from the memory cell array and writing data to the array is a limiting factor, both of which are heavily affected by the particular architecture for transferring read and write data signals to and from the memory cell array. Dynamic random access memories (DRAMs) represent a particularly dense form of integrated circuit memory in which a large amount of storage can be provided within a small area of an integrated circuit, making DRAMs an attractive option for low-cost, electronic memory, whether provided in a separate chip, or as an embedded memory of a system-on-a-chip (SOC) integrated circuit.
Static random access memories (SRAMs) have generally faster access times than DRAMs, but are much less dense than DRAMs, because SRAMs require a minimum of six transistors per memory cell, all of which extend in the plane of the integrated circuit chip. On the other hand, DRAMs require only one transistor per memory cell, which is oriented vertically in state of the art DRAMs to conserve chip area. It is apparent that in order for DRAMs to compete effectively with fast access time (SRAM), especially in SOC integrated circuits, that DRAMs must provide fast access to stored information, while preserving advantages over SRAM as to density and quantity of storage.
Moreover, recently, there has been a trend towards hybrid types of memory. For example, a content addressable memory can be designed having storage cells composed of one transistor-one capacitor cells similar to that of dynamic random access memories. In addition, other than DRAMs, other types of memories have utilized architecture similar to that of DRAMs as a method of reading and writing to storage cells of the memory, namely, in that data signals are transferred to and from storage cells and an external interface of the memory by way of a series of sense amplifiers.
Conventional integrated circuit memories utilize separate read and write data buses. These solutions occupy larger silicon area and impede aggressively dense chip/macro targets.
As illustrated in
FIGS. 1A and 1B
, a conventional configuration for a multi-banked DRAM is shown, which can be either a stand-alone memory, or an embedded DRAM macro within a larger chip. As shown in
FIG. 1A
, the multi-banked DRAM includes a plurality of banks BANK<
0
> through BANK<
15
>, and a write driver
12
, and an off-chip driver
14
. As shown in the inset of
FIG. 1B
, each bank of the DRAM
10
, for example, BANK<xx>, includes a storage cell array
16
, at least one first sense amplifier block
18
having a plurality of first sense amplifiers, and at least one local buffer block having a plurality of local buffers
20
. The purpose of the sense amplifiers of the first sense amplifier block
18
is to transfer signals to and from storage cells of the storage cell array
16
on respective bitline pairs (BLP) of a plurality of bitline pairs. Transfer of signals between the sense amplifiers of the first sense amplifier block
18
and the block
20
of local buffers is performed as follows. The read output signals of a number of sense amplifiers of the first sense amplifier block, for example four, or eight sense amplifiers, are multiplexed into a local buffer block
20
as selected by column select lines (CSL) and the write input signals to that same number of sense amplifiers of the first sense amplifier block are demultiplexed out of the local buffer block
20
as selected by the column select lines (CSL), respectively. The input and output signal lines of the local buffer block
20
, in turn, are multiplexed onto read primary data lines RPDL, and demultiplexed from complementary write primary data lines WPDLt and WPDLc, respectively. As shown in
FIG. 1A
, these input output buses: the read primary data lines and the write primary data lines run the length of the memory
10
over all of the banks to further circuitry within off-chip driver
14
and write driver
12
which handle the transfer of write data signals to and from the memory
10
. The read primary data line (RPDL) is connected to an off-chip driver block
14
, while the write primary data lines (WPDLc and WPDLt) originate from the write driver
12
.
Operation of the conventional DRAM
10
varies as to whether data is being read from or written to an array of the memory
10
, in that separate read and write buses are used for reading data from, and writing data to the memory
10
. A read/write control signal (WR/RDN) is provided for controlling whether the array
16
is read from or written to. In read mode, a data bit from a storage cell of the array
16
is transferred via a first sense amplifier of FSA block
18
to a local buffer of LBF block
20
. From there, an amplified data signal is transferred onto the RPDL bus, from which the signal is further transferred to an off-chip driver block
14
. In write mode, the data to be written into a storage cell of an array
16
is provided to a write driver
12
of the memory
10
. From there, the data bit is transmitted onto the write primary data lines WPDLt and WPDLc and through the LBF
20
to the first sense amplifier blocks
18
.
FIG. 2
is a schematic diagram illustrating a conventional arrangement for a local buffer
22
, such as that used in LBF block
20
of DRAM
10
. As illustrated, local buffer
22
provides output onto a read primary data line RPDL, which is separate from the lines on which write input is received, WPDLc and WPDLt. Local buffer
20
includes a cross-coupled pair of p-type field effect transistors (PFETs) P
3
and P
4
, which act to drive the fan nodes FT and FC to complementary levels. Fan nodes FT and FC typically carry data signals which are multiplexed with respect to the storage cell array
16
of the memory
10
, and which are demultiplexed as data signals are transferred to one of several first sense amplifiers with which the particular local buffer
20
is selectively switched. In addition, a pair of precharge PFETs P
1
and P
2
are provided for precharging the fan nodes FT and FC to the supply voltage between successive read or write cycles when the voltage at node PCN is driven low. In addition, a pair of pull-up PFETs P
5
and P
6
are provided to drive the voltage of a respective one of the fan nodes FT and FC up to a supply voltage, according write input received on complementary lines WPDLt and WPDLc. A device N
3
is provided for controlling whether a read or write operation is to be performed. Specific read circuitry including NOR gates O
1
and O
2
, inverter I
1
, and the output driver including PFET P
7
and NFET N
4
, convert complementary read data on fan nodes FT and FC to a single output signal at RDPL.
Operation of the local buffer
22
proceeds as follows. Prior to a read or a write operation, the fan nodes FT and FC are precharged to a given potential such as a supply voltage VDD when the voltage at PCN is driven low. At that time, the primary read data line, RPDL, is tri-stated. The read operation begins such that a data signal from a storage cell of the array
16
appears on a bitline coupled thereto, and a first sense amplifier of FSA block
18
is then activated. The first sense amplifier amplifies a small voltage difference between the bitline and a complementary reference bitline to rail-to-rail complementary signals having a voltage difference of about 1V to 2V, depending upon the technology. In a typical DRAM
10
, column select circuitry then selects the output of a particular first sense amplifier of a group of typically four or eight first sense amplifiers
Golz John W.
Hanson David R.
Kim Hoki
International Business Machines - Corporation
Neff Daryl K.
Phan Trong
Schnurmann H. Daniel
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