Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2002-04-12
2004-08-31
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
Reexamination Certificate
active
06784029
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to ESD protection devices. More particularly, it relates to ESD protection devices that are implemented using BiCMOS technology.
BACKGROUND OF THE INVENTION
Analog circuits typically display sensitivity to excessive voltage levels. Transients, such as electrostatic discharges (ESD) can cause the voltage handling capabilities of the analog circuit to be exceeded, resulting in damage to the analog circuit. ESD protection devices have, therefore, been devised to shunt current to ground during excessive voltage peaks.
In the case of BiCMOS output interface circuits that allow dual polarity of the output voltage amplitude (so-called “swing”), conventional triggering ESD structures such as SCRs, LVTSCRs, GGNMOS, TFO devices and even diode pairs are unsuitable. When these devices are reverse biased or a reverse power supply is applied, a substantial amount of power is consumed by the internal diode structure, as is discussed in greater detail below.
The ESD protection device or triggering structure for dual polarity applications should therefore display an S-shaped I-V characteristic for voltage swings in both directions. Bi-directional thyristor devices such as TRIACs (triode AC switches) and DIACs (diode AC switches) (for example AC trigger diodes and bi-directional p-n-p-n diode switches) exist that provide for bi-directional voltage swings. However, ESD protection devices require specific functional specifications in order to operate within a specific window. The triggering voltage may not be too high, to avoid damage to the circuit being protected. Also, the triggering structure must not remain in conduction once the ESD pulse has passed and normal voltages resume. Thus, the holding voltage of the device must be sufficiently high to avoid latch-up during normal operation. Furthermore, in the case of integrated circuits based on BiCMOS technology it is desirable to implement the protection circuit using existing process steps.
The present invention therefore provides a triggering ESD structure that can readily be implemented in BiCMOS technology and which provides for bi-directional voltage swings.
SUMMARY OF THE INVENTION
The present invention provides a BiCMOS ESD protection device with dual voltage capabilities. This is achieved by providing two laterally spaced p-regions in a n-material and defining a n+ region and a p+ region connected by a common contact, in each of the p-regions. In this way a device is defined that has I-V characteristics that are similar to those defined by a SCR device in a positive direction, but, in this case, having those characteristics in both directions. The device may be asymmetrical to accommodate different voltage amplitudes in the positive and negative directions.
According to the invention, there is provided an ESD protection structure having
a first p-region formed in a n-material; a second p-region formed in the n-material and laterally spaced from the first p-region; a first n+ region and a first p+ region formed in the first p-region, and connected by a first common contact, and a second n+ region and a second p+ region formed in the second p-region, and connected by a second common contact One or both of the p-regions may comprises a p-deep region, a p-well, or a P-body. A shallow trench isolation region or thick field oxide may be formed between the first p-region and the second p-region. Furthermore, a sinker region may be formed between the first p-region and the second p-region.
Further, according to the invention, there is provided a method of forming a bi-directional ESD protection device, comprising providing a semiconductor substrate, n-doping at least part of the semiconductor substrate to form n-material, masking and doping the n-material to define a first and a second p-region in the n-material that are laterally spaced from each other, forming a n+ region and a p+ region laterally spaced from each other, in each of the two p-regions, and providing a common contact for both of the n+ region and p+ region of the two p-regions. Ideally BiCMOS technology is used in the process steps. Typically the n+ region and p+region in each of the p-regions are formed by masking and doping the p-regions. The p-regions may be defined by one or more of a p-well, p-body, collector, or p-deep type implant. The method may include n-doping the region between the p-regions to define a higher doped region between the p-regions, for example, forming a sinker region between the p-regions. The size and location of the higher doped region between the p-regions may be chosen to achieve desired triggering and holding voltage characteristics for the device. The method may further include forming one or more ISO, NBL, or lightly doped regions in the n-material. Also, the first p-region may be different from the second p-region to define an asymmetrical structure. This difference in the p-regions may be in one or more of the doping level, thickness, and width of the p-regions.
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Beek Marcel ter
Concannon Ann
Hopper Peter J.
Vashchenko Vladislav
Fourson George
Jurgen Vollrath
National Semiconductor Corporation
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