Bi-directional double NMOS switch

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device

Reexamination Certificate

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Details

C327S365000

Reexamination Certificate

active

10532922

ABSTRACT:
A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved compared to prior art switches. Pumping the gates to higher voltages may cause a further reduction of the sizes of the NMOS transistors. In addition, advantageously, a large range of input and output voltages can be allowed between the sources of the NMOS transistors, whereby the sources act as input and output respectively of the switch, thus allowing application of the switch in a broad technical field.

REFERENCES:
patent: 5705911 (1998-01-01), Tamai
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patent: 5789900 (1998-08-01), Hasegawa et al.
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patent: 5939908 (1999-08-01), Moore et al.
patent: 6548916 (2003-04-01), Kanazawa et al.
patent: 6683393 (2004-01-01), Lewis
patent: 7030591 (2006-04-01), Stellberger
patent: 0362080 (1990-04-01), None
patent: 1091490 (2000-09-01), None
patent: 1079525 (2001-02-01), None
patent: 1119572 (1999-07-01), None

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