Bi-directional capable bucket brigade circuit

Details Bi-directional capable bucket brigade circuit Bi-directional capable bucket brigade circuit

2000-01-07

2004-07-13

Vu, Ngoc-Yen (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

C348S308000

Reexamination Certificate

active

06762795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuits useful in processing the output of image sensing arrays. More specifically, the present invention relates to Time Delay Integration (“TDI”) circuits useful in processing the output of image sensing arrays.
2. Description of the Related Art
The Time-Delay-Integration (“TDI”) architecture is typically found in high speed digital image sensing devices such as Charge Coupled Device (“CCD”) image sensors to achieve satisfactory sensitivity. It has utility with many various types of image sensing arrays variously sensitive to, for example, the infrared, visible light, and X-ray wavelengths. In an image sensing device with a TDI architecture, an image is optically scanned so that each part of the image is sensed with different parts, typically lines, of the image sensing array in a synchronized, delayed manner. The plural outputs over time of the image sensing array for each part of the image are summed, thereby improving the sensitivity and spatial resolution of the image sensing device. One measure of performance of image sensing devices is the Modulation Transfer Function (“MTF”), which is defined as the ratio of the modulation of the output signal to the modulation of the input signal, versus spatial frequency.
Typically, the TDI circuits are implemented in a type of silicon-based integrated circuit known as a Read-Out Integrated Circuit (“ROIC”), which is combined with the sensing array to form a Sensor Chip Assembly (“SCA”). SCAs are used in a variety of digital imaging systems, including, for example, night vision cameras, surveillance cameras, remote imaging cameras, and manufacturing line inspection cameras, and are suitable even for standard army dewar assembly (“SADA”) type applications and three color activities. Multiple color band activities are scanning systems which incorporate more than one spectral band, or color, on a SCA. Each of the colors is defined by a bank of sensing elements on which a single spectral color is incident. SCAs are particularly useful when the sensing array is made of a non-silicon semiconductor material, which is typical because non-silicon semiconductor materials are inherently sensitive to various useful portions of the electromagnetic spectrum. Image information in the form of electrical charge is produced in the imaging array. The charge is collected and processed by the typically silicon-based ROIC. SCAs are manufactured using a variety of well known techniques, ranging from fabricating the sensing array separately from the ROIC and mounting the sensing array and ROIC on a common substrate or a common printed circuit board, to mounting the sensing array substrate on the ROIC substrate and then fabricating the sensing array.
TDI has been performed with both voltage transfer devices and charge transfer devices. Charge coupled devices (“CCDs”) transfer charge by modulating the surface potential in a semiconductor. For example, time delay integration may be performed in a SCA TDI architecture using a CCD array in a “side rider” configuration. Bucket brigade devices (“BBDs”) move charge by utilizing the threshold barrier formed by MOSFETs. Time delay integration can be implemented using standard bucket brigade (“BBD”) circuits.
CCDs and BBDs preferably should have a bidirectional capability for certain types of applications such as, rotating mirror scanning arrays. The conventional approach to achieve bi-directionality has been to use two bucket brigade structures, one for each direction, or two CCDs, or two CCDs with switched or reconfigurable inputs, which read the unit cell outputs. The use of reconfigurable inputs requires multiplexer circuitry to place the unit cell outputs onto a single column bus, a programmable clock to synchronize the column bus output to the CCD bucket inputs, and demultiplexer circuitry to place the synchronized column bus signal into the CCD buckets. The increased amount of additional circuitry used to achieve bi-directionality in these conventional approaches is undesirable.
Hence, a need exists in the art for a TDI circuit that is useful for bidirectional processing of the output of image sensing arrays without using switched or reconfigurable inputs, and that has reduced ROIC circuitry relative to the ROIC circuitry required in the side rider CCD implementation.
SUMMARY OF THE INVENTION
The need in the art is addressed by the present invention, which in one embodiment is a time delay integration circuit comprising a plurality of serially coupled circuit groups, each comprising at least; a first charge transfer path segment having first and second serially coupled gates; a second charge transfer path segment having first and second serially coupled gates, the first gate of the second charge transfer path being coupled to the second gate of the first charge transfer path; a first capacitor having a first terminal coupled to the first gate of the first charge transfer path segment and a second terminal; and a second capacitor having a first terminal coupled to the first gate of the second charge transfer path segment and a second terminal; a plurality of imaging sensor unit cell inputs controllably coupled, respectively, to the first terminals of the second capacitors; a screen voltage node controllably coupled in a first circuit mode to the first gates and in a second circuit mode to the second gates; a first phase clock node coupled to the second terminals of the first capacitors and controllably coupled in the first circuit mode to the second gates of the second charge transfer path segments and in the second circuit mode to the first gates of the first charge transfer path segments; and a second phase clock node coupled to the second terminals of the second capacitors and controllably coupled in the first circuit mode to the second gates of the first charge transfer path segments and in the second circuit mode to the first gates of the second charge transfer path segments.
Another embodiment of the invention is a two sample per dwell time delay integration circuit comprising a plurality of serially coupled circuit groups, each comprising a first charge transfer path segment having first and second serially coupled gates; a first capacitor having a first terminal coupled to the first gate of the first charge transfer path segment and a second terminal; a second charge transfer path segment having first and second serially coupled gates, the first gate of the second charge transfer path being coupled to the second gate of the first charge transfer path; a second capacitor having a first terminal coupled to the first gate of the second charge transfer path segment and a second terminal; a third charge transfer path segment having first and second serially coupled gates, the first gate of the third charge transfer path being coupled to the second gate of the second charge transfer path; a third capacitor having a first terminal coupled to the first gate of the third charge transfer path segment and a second terminal; a fourth charge transfer path segment having first and second serially coupled gates, the first gate of the fourth charge transfer path being coupled to the second gate of the third charge transfer path; and a fourth capacitor having a first terminal coupled to the first gate of the fourth charge transfer path segment and a second terminal; a plurality of imaging sensor unit cell inputs controllably coupled, respectively, to the first terminals of the second capacitors; a screen voltage node controllably coupled in a first circuit mode to the first gates and in a second circuit mode to the second gates; a first phase clock node coupled to the second terminals of the first and third capacitors and controllably coupled in the first circuit mode to the second gates of the second and fourth charge transfer path segments and in the second circuit mode to the first gates of the first and third charge transfer path segments; and a second phase clock node coupled to the second terminals of the second and fourth cap

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