Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – Having selection between plural continuous waveforms
Reexamination Certificate
2002-05-28
2004-10-12
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
Having selection between plural continuous waveforms
C327S298000
Reexamination Certificate
active
06803796
ABSTRACT:
BACKGROUND OF THE INVENTION
(a). Field of the Invention
The present invention relates to a phase switch circuit. Especially, the present invention relates to a phase switch circuit that can switch bi-directionally and avoid glitch/spike.
(b). Description of the Prior Arts
In a data recovery system, the high frequency of the received signal that declining and impacted by the noise of media will be recovered by a equalizer, however, a correct sampling of data stream still depends on a precise clock. The rising/falling edge of the clock needs to align precisely to the middle of data stream to obtain correct sampling. In prior art, a data recovery system employs a continuous time Phase-Locked Loop (PLL) to complete the job of clock recovery, and with which align with the data stream received and the sampling clock. The disadvantages of clock recovery that employing the continuous time PLL are as follows: (1) longer lock time (2) influence of phase noise (3) only providing one receive channel.
In current trend of technology, the multiple phase system will be adapted to handle the clock recovery that described above. With the switch of phase signal, the proper phase signal being selected in the multiple phase system will make the rising/falling edge of the recovered sampling clock align preciously to the middle of the data stream, which will theoretically make bit error rate to the minimum level. The rapid lock-in is the advantage of using the switch of multiple phases to handle the clock recovery, that is, the lock-in will be completed only in few clock cycle, and since most calculation is in digital format, the influence of noise will be avoided to increase the yield, more over, the multiple phases clock will provide multiple receive channels to be shared concurrently.
The clock recovery system that employing the multiple phases is shown in the FIG.
1
(
a
), the received data stream and the system's clock will be processed by a digital signal processor
10
(DSP) to obtain the information of the relative time of the clock and the data stream, and the information will be used to determine whether the clock ahead or behind the best point of sampling, thereafter, a up/down switching signal will be sent to the multiple phases switching circuit
11
to switch the output of different phases clock., with this mechanism the proper recovered clock will be generated and the latch
12
will complete the sampling and output the received data. The FIG.
1
(
b
) is showing the diagram of the clock of the system described above, the system will obtain 8 multiple phases clock (ck
0
-ck
7
) that spreading evenly on 360 degree, the data stream in the figure is showing the time frame of receiving data, as shown, the best clock for sampling is ck
4
whose rising edge aligning preciously to the middle of two consecutive rising/falling edge of the received data, which makes the bit error rate low down to the minimum level. The operation in the FIG.
1
(
a
) is showing a example, if the wave of the recovery clock that outputting from the multiple phases switching circuit
11
is same as the one shown in FIG.
1
(
c
), that is, the rising edge of the starting clock is aligning to ck
2
, and then switching to ck
3
and ck
4
sequentially thru the process of the digital signal, and finally locking on the ck
4
, then, the clock recovery eventually being completed. However, the example in FIG.
1
(
c
) is a better one in clock recovery, in practice, the glitch/spike that caused by the control signal of phase switching in different time frame is ought to be taken into account, as shown in the FIG.
1
(
d
), if special attention has not been paid in the time of switching, the glitch/spike
13
will appear in clock recovery and cause error sampling. The major feature in clock recovery system is that the switching phase has to move upward or downward (positive phase or negative phase), since the starting phase can be ahead or behind the idealist phase. In prior art, in order to avoid the glitch/spike, the phase switch technology only switch one direction, for the multiple phases clock is spreading evenly on 360 degrees, one direction switching still can switch to the phase properly, however, in the application of clock recovery, one direction switching will increase the average lock-in time; for example, in a positive phase one direction switching circuit, if the proper phase is the adjacent negative phase, the phase switcher needs to switch almost 360 degrees toward the positive phase to reach the target negative phase, the data selected in the process of sampling will not be assured to be correct; the application is pretty limited.
More, the phase switching circuit is not only employed in the data recovery system, but also in a fractional-N frequency synthesizer. A conventional fractional-N frequency synthesizer accomplish the frequency synthesizing by swallow a pulse in a fixed time, as shown in FIG.
2
(
a
) the system is comprising the phase detector
20
, the charge pump
22
, the voltage control oscillator
23
and the pulse swallow
24
. The corresponding clock diagram is shown in FIG.
3
(
b
), the original clock is shown in FIG.
3
(
a
), the original clock frequency is f
1
=1/Ts, if a pulse is swallowed in time of Tp, which will be equivalent to the output frequency f
1
−(1/Tp) of the voltage control oscillator
22
, with the control of length of the time of Tp, the non-integer multiple of f
1
(reference frequency) can be synthesized, conventionally, a counter can be used to accomplish this function. But, since swallowing a pulse directly will cause a bigger clock jitter on clock signal, the multiple phase clock signal will be employed to swallow a pulse gradually in modern circuit design in order to low down the clock signal jitter caused by the sudden change of frequency. A practical example is to accomplish the all 360 degree phase switching within a certain time period, that is, to switch sequentially a complete phase within few cycles, and with which swallow a pulse gradually. The system shown in FIG.
2
(
b
) is employing the multiple phase clock signal to swallow a pulse gradually, the difference that differing from the FIG.
2
(
a
) is that the voltage control oscillator
23
and the pulse swallow
24
are replaced by the multiple voltage control oscillator
25
and the multiple phase switching circuit
21
, within, a up/down switching signal is adapted to control the multiple phase switching circuit and further switch the output of different phase clock. The corresponding diagram of clock is shown in FIG.
3
(
c
), the original clock is shown in FIG.
3
(
a
), the original clock frequency is f
1
=1/Ts, if one fourth of a pulse is swallowed within every 3 clock cycles (
3
Ts) in time of Tp, a entire pulse will be swallowed within 12 clock cycles, which will be equivalent to the output frequency f
1
−(1/Tp) of the voltage control oscillator
22
, with the control of the time length of Tp, the non-integer multiple of f
1
(reference frequency) can be synthesized.
The operation of sequential phases switching is essential in the fractional-N frequency synthesizer described above. Therefore, to avoid the glitch/spike in phase switching is a major consideration of circuit design, in the application of clock recovery, the occurrence of glitch/spike will cause data sampling error, also the bit error rate increase; and in the application of fractional-N frequency synthesizer, the glitch/spike will response for bigger phase noise. How to avoid the glitch/spike in phase switching is a key issue when a designer designing circuit.
To this end, the primary purpose of the present invention is to develop a phase switching circuit that will switch forward/backward bi-directionally in phase switching and will avoid the glitch/spike when any time enabling the signal switching.
SUMMARY OF THE INVENTION
The primary aspect of the present invention is to provide a multiple phases switching circuit, which can be used in a multiple phase signal generator and a succeeding circuit, in t
Chiu Pao-Cheng
Huang Chen-Chih
Lam Tuan T.
Realtek Semiconductor Corp.
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