Bi-CMOS type of semiconductor memory device

Details Bi-CMOS type of semiconductor memory device Bi-CMOS type of semiconductor memory device

1988-02-16

1990-01-30

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518911, G11C 1134

Patent

active

048978205

ABSTRACT:
An address buffer decoder comprises n address buffer circuits, a decoder circuit, 2.sup.n level converting circuits and 2.sup.n driver circuits. Each of the address buffer circuits has an input terminal receiving an address signal of an ECL level. The decoder circuit comprises a plurality of output terminals and a plurality of inverted output terminals in each of the address buffer circuits and a plurality of interconnections. A selecting signal of an "L" level is outputted to one of the plurality of interconnections depending on combinations of address signals inputted to the plurality of address buffer circuits. The selecting signal is converted into a signal of an MOS level by each of the level converting circuits. Current of the signal of the MOS level is amplified by each of the driver circuits. The signal of the MOS level is outputted to a corresponding selecting line.

REFERENCES:
patent: 4369503 (1983-01-01), Isogai
patent: 4745582 (1988-05-01), Fukushi et al.
patent: 4757474 (1988-07-01), Fukushi et al.
IEEE Journal of Solid-State Circuits, "13-ns, 500-m W, 64-kbit ECL RAM Using HI-BICMOS Technology" by K. Ogiue et al., vol. SC-21, No. 5, Oct. 1986, pp. 681-684.

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