Bi-CMOS semiconductor device immune to latch-up

Details Bi-CMOS semiconductor device immune to latch-up Bi-CMOS semiconductor device immune to latch-up

1986-11-13

1989-04-25

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 55, 357 86, 307446, H01L 2702

Patent

active

048252743

ABSTRACT:
A circuit including a Bi-CMOS semiconductor device of a structure capable of preventing the latch-up phenomenon from occurring when operated as an inverter or the like. The semiconductor device includes a MOS FET and a bipolar transistor merged with each other and having a PNPN or NPNP structure in a region to which minority carriers can migrate through diffusion and in which a same potential is applied to at least a pair of P-type and N-type regions or a backward voltage is applied across PN junctions in operation. The semiconductor device comprises electrodes provided in both P-type and N-type regions, respectively, which form one of the PN junctions, wherein a backward voltage not lower than 0.5 V is applied across the electrodes upon operating the device.

REFERENCES:
patent: 4628341 (1986-12-01), Thomas
patent: 4661723 (1987-04-01), Masuda et al.

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