Bi-CMOS semiconductor device having memory cells formed in isola

Details Bi-CMOS semiconductor device having memory cells formed in isola Bi-CMOS semiconductor device having memory cells formed in isola

1990-02-16

1991-12-24

Hille, Rolf

357 42, 357 48, H01L 2702

Patent

active

050757520

ABSTRACT:
A Bi-CMOS semiconductor device includes a P-type semiconductor substrate, an N-type buried layer formed in the semiconductor substrate, a P-type well region formed on the buried layer, and an N-channel MOS transistor formed in a first predetermined area of the well region. The Bi-CMOS semiconductor device further includes an N-type surrounding layer formed to surround the well region in cooperation with the buried layer. The surrounding layer electrically isolates the well region from the substrate and the other P-type well region.

REFERENCES:
patent: 4327368 (1982-04-01), Uchida
patent: 4862240 (1989-08-01), Watanabe et al.
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4887142 (1989-12-01), Bertotti et al.
U.S. Ser. No. 216,045 filed Jul. 7, 1988, abandoned.
U.S. Ser. No. 343,302 filed Apr. 26, 1989.

Affiliated with

Also associated with

Rating

Bi-CMOS semiconductor device having memory cells formed in isola does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bi-CMOS semiconductor device having memory cells formed in isola, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bi-CMOS semiconductor device having memory cells formed in isola will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-47547