Bi-CMOS out buffer circuit for CMOS logic

Details Bi-CMOS out buffer circuit for CMOS logic Bi-CMOS out buffer circuit for CMOS logic

1991-11-29

1993-09-21

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307446, H03K 19092, H03K 1902

Patent

active

052472140

ABSTRACT:
A semiconductor logic circuit includes a CMOS logic circuit having a first input terminal and first and second MOSFETs serially connected between a power source and a ground. The connection point of the first MOSFET to the second MOSFET serves as a first output terminal. The gates of the first and second MOSFETs are connected to the first input terminal. A partial circuit has second and third input terminals. Third and fourth MOSFETs are serially connected between the power source and ground. A connection point of the third MOSFET to the fourth MOSFETs serves as a second output terminal. The second and third input terminals are connected to the first input terminal and to the first output terminal, respectively. A fifth MOSFET is connected between the power source and the second output terminal and has a gate connected to the first output terminal. And a bipolar transistor and a sixth MOSFET are serially connected between the power source and ground. The bipolar transistor has an input terminal connected to the second output terminal. The sixth MOSFET has an input terminal connected to the first output terminal. And the common connection point of the sixth MOSFET to the bipolar transistor serves as an output terminal of the semiconductor logic circuit.

REFERENCES:
patent: 4558234 (1985-12-01), Suzuki et al.
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4926069 (1990-05-01), Yamazaki
patent: 5043600 (1991-08-01), Horiuchi
patent: 5047669 (1991-09-01), Iwamura et al.

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