Bi-CMOS logic circuit with inverter feedback for high speed

Details Bi-CMOS logic circuit with inverter feedback for high speed Bi-CMOS logic circuit with inverter feedback for high speed

1993-01-06

1994-01-11

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307443, H03K 1902, H03K 1908

Patent

active

052784630

ABSTRACT:
It is purposed to ensure both high speed operation and low power consumption in an output section of a Bi-CMOS type TTL logic circuit. For this purpose, impedances of a base driving part (a series circuit of a MOS transistor 9 and a resistor 11) and a collector driving part A (a resistor 12) of a bipolar transistor 1 are brought into low impedances only when the bipolar transistor 1 is changed from an off-to on-state thereof. To achieve the just-mentioned operation, potential on an output 30 is detected by an inverter 16 and on the basis of an output from the inverter 16 both MOS transistors 17, 19 are on-controlled to substantially short-circuit the resistors 11, 12. When the transistor 1 stays at its on-state, both transistors 17, 19 have been switched off, so that base and collector currents of the transistor 1 have been conducted through the resistors 11, 12 to permit the resistors 11, 12 to be greater. Thus, low power consumption is attained.

REFERENCES:
patent: 5001365 (1991-03-01), Murabayashi et al.
patent: 5057713 (1991-10-01), Iwamura et al.
patent: 5118972 (1992-06-01), Wissel et al.
patent: 5173623 (1992-12-01), Chau et al.
patent: 5191240 (1993-03-01), Fleischer
"A Subnanosecond BI-CMOS Gate-Array Family", Hiroshi NAKASHIBA et al., IEEE 1986 Custom Integrated Circuits Conference, CH2258-2/86/000-0063, pp. 63-66.

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