Bi-CMOS logic circuit

Details Bi-CMOS logic circuit Bi-CMOS logic circuit

1987-05-21

1989-03-28

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307570, 307574, 307581, H03K 1902, H03K 19094, H03K 1760

Patent

active

048167053

ABSTRACT:
A complementary logic circuit which has large power handling capacity, high switching speed and still has low power consumption is disclosed. The circuit is composed of a first stage comprising a complementary MIS-FET, and an output stage comprising complementary bipolar transistors or complementary vertical FETs. The output stage is provided with pull-up and pull-down elements, which pull up or pull down the amplitude of the output signal almost equal to that of the power supply voltages. Accordingly, the lack of sufficient amplitude in the conventional Bi-MIS circuit to drive the C-MIS circuit is improved, and it secures the stable operation of C-MIS logic circuits.

REFERENCES:
patent: 3649851 (1972-03-01), Cohen
patent: 3879619 (1975-04-01), Pleshko
patent: 4021684 (1977-05-01), Macey
patent: 4103188 (1978-07-01), Morton
patent: 4129879 (1978-12-01), Tantraporn et al.
patent: 4209713 (1980-06-01), Satov et al.
patent: 4365316 (1982-12-01), Iwahashi et al.
patent: 4532439 (1985-07-01), Koike
Patent Abstract of Japan, vol. 4, No. 8 (E166), Jan. 22, 1980, p. 103 E 166; and JP-A-54 148469 (Oki Denki Kogyo K.K.) 20-11-1979.
Patent Abstract of Japan, vol 5, No. 3 (E-40)[675], Jan. 10, 1981 and JP-A-55 134960, (Daini Seikosha K.K.) 21-10-1980.

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