Bi-CMOS logic circuit

Details Bi-CMOS logic circuit Bi-CMOS logic circuit

1990-05-18

1992-03-17

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307570, 307451, H03K 19013, H03K 19082, H03K 19003, H03K 19094

Patent

active

050971506

ABSTRACT:
A Bi-CMOS logic circuit includes a Bi-CMOS circuit which is composed of first and second bipolar transistors, first and second resistors, and first and second MOS transistors. An input signal is applied to the gates of the first and second MOS transistors, and an output signal is drawn from a connection node at which the first and second bipolar transistors are connected in series between first and second power sources. A third MOS transistor is connected between the collector and emitter of the first bipolar transistor. The input signal is applied to the gate of the third MOS transistor. In place of or in addition to the third MOS transistor, a fourth MOS transistor is provided which is connected between the collector and emitter of the second bipolar transistor. The third and fourth MOS transistors function to decrease roundings of rising and falling edges of the waveform of the output signal.

REFERENCES:
patent: 4683384 (1987-07-01), Shibata et al.
patent: 4694202 (1987-09-01), Iwamura et al.
patent: 4719373 (1988-01-01), Masuda et al.
patent: 4804868 (1989-02-01), Masuda et al.
patent: 4806797 (1989-02-01), Yamazaki
patent: 4948990 (1990-08-01), Shin et al.
patent: 4965470 (1990-10-01), Shin

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