Bi-CMOS logic circuit

Details Bi-CMOS logic circuit Bi-CMOS logic circuit

1990-01-09

1990-12-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307263, 307570, 307572, 307270, H03K 1902, H03K 1716, H03K 512

Patent

active

049773372

ABSTRACT:
A Bi-CMOS logic circuit structured by bipolar transistors and insulated gate type transistors includes a first NPN bipolar transistor for charging an output node and a second NPN bipolar transistor for discharging the output node. The first bipolar transistor has a collector coupled to a first power supply and an emitter connected to the output node. The second bipolar transistor has a collector connected to the output node and an emitter coupled to a second power supply. The Bi-CMOS logic circuit also includes at least one P channel insulated gate type transistor provided between the first power supply and a base of the first bipolar transistor for receiving an input signal at its gate, and at least one N channel insulated gate type transistor provided between the output node and a base of the second bipolar transistor for receiving the input signal at its gate. The Bi-CMOS logic circuit further includes a third NPN bipolar transistor for drawing charges out of the base of the first bipolar transistor, and an impedance element for biasing the base of the second bipolar transistor relative to the second power supply. The third bipolar transistor has a collector connected to the base of the first bipolar transistor, a base connected to the base of the second bipolar transistor and an emitter connected to the second power supply. The impedance element includes a fourth N channel insulated gate type transistor having a gate connected to the output node, one conduction terminal connected to the respective bases of the second and third bipolar transistors, and other conduction terminal coupled to the second power supply.

REFERENCES:
patent: 4845386 (1989-07-01), Veno
Yoji Nishio et al., "A BiCMOS Logic Gate with Positive Feedback", Digest of Technical Papers of 1989 IEEE International Solid-State Circuits Conference, Feb. 16, 1989, pp. 116-117, 305.
A. Watanabe et al., "High Speed BiCMOS VLSI Technology With Buried Twin Well Structure", Digest of Technical Papers of IEDM 85, 1985, pp. 423-426.

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