BI-CMOS clock driver with reduced crossover current

Details BI-CMOS clock driver with reduced crossover current BI-CMOS clock driver with reduced crossover current

1989-06-26

1990-10-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307456, 307263, 307570, 307270, H03K 1902, H03K 19088, H03K 512

Patent

active

049654713

ABSTRACT:
The present circuit is intended for use in providing CCD phase clocks. It has the benefit of reduced crossover currents which in turn reduces power consumption and device size requirements.
The circuit is comprised of a pair of folded cascode CMOS amplifier input stages, a pair of bipolar output stages containing vertical NPN transistors, and 2 PMOS sense transistors for each output stage for reducing the crossover current which occurs when switching output stages. These sense transistors reduce the power consumption of the circuit and the size of the transistors necessary for the output.
The input stage has the capability of operating from TTL or ECL signal inputs by selecting an input reference voltage. The folded cascode configuration also provides the level shifting necessary for inputs to the output stage's NPN transistors.
The sense transistors provide feedback in the form of the charge stored in the output transistors to prevent a pair of output transistors from turning on prior to the other pair turning off.

REFERENCES:
patent: 4456837 (1984-06-01), Schade, Jr.

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