Bi-CMOS circuit with high-speed active pull-down output currents

Details Bi-CMOS circuit with high-speed active pull-down output currents Bi-CMOS circuit with high-speed active pull-down output currents

1990-10-30

1992-06-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307570, H03K 1704

Patent

active

051245825

ABSTRACT:
A Bi-CMOS circuit according to the present invention includes a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to the base of an output transistor when the first transistor is turned on, and an active pull-down current supplying means connected to the gate electrode of the first transistor. The active pull-down current supplying means provides a second current, which is an active pull-down current, to the base of the output transistor so that the first and second currents can be supplied to the base of the output transistor.

REFERENCES:
patent: 4645952 (1987-02-01), van Tran
patent: 4697103 (1987-09-01), Ferris et al.
patent: 4704548 (1987-11-01), Strong et al.
patent: 4739198 (1988-04-01), Maruyama
patent: 4829201 (1989-05-01), Masuda et al.
patent: 4845386 (1989-07-01), Ueno
patent: 4902914 (1990-02-01), Masuoka
patent: 4970414 (1990-11-01), Ruth, Jr.
patent: 4975600 (1990-12-01), Tran et al.
patent: 4999523 (1991-03-01), Cham et al.
Patent Abstracts of Japan, vol. 7, No. 218 (E-200) [1363], Sep. 28, 1983, and JP-A-58 111 525.

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